Re: [PATCH 2/2] arm64: dts: qcom: nord: add CoreSight debug nodes

[Jie Gan]

On 10/15/2026 10:18 PM, Konrad Dybcio wrote:
> On 9/22/26 12:08 PM, Shawn Guo wrote:
> > From: Jie Gan <jie.gan@xxxxxxxxxxxxxxxx>
> >
> > Add the CoreSight trace topology for the Qualcomm Nord SoC: CTCU, STM,
> > TPDM/TPDA sources and aggregators, funnels, replicators, TMC ETR/ETF
> > sinks, TNoC/ITNoC nodes and per-subsystem CTIs. This wires up trace
> > sources for SOCCP, BCV/IMH/DPM, GCC, QM, DL_NOC, the CDSP NSP0-3
> > clusters, DLMM, EVA, MDSS0/1, LPASS and the AOSS SWAO priority TPDMs,
> > plus the DDR0-3 channel and LLCC TPDMs, all funneled through the
> > tn_ag aggregator into the main CoreSight funnel and out to the AOSS
> > sink.
>
> [...]
>
>
> > +		tpdm@12410000 {
> > +			compatible = "qcom,coresight-tpdm", "arm,primecell";
> > +			reg = <0x0 0x12410000 0x0 0x1000>;
> > +
> > +			clocks = <&aoss_qmp>;
> > +			clock-names = "apb_pclk";
> > +			label = "tpdm_ddr3_llcc_2";
> > +
> > +			qcom,cmb-element-bits = <32>;
> > +			qcom,cmb-msrs-num = <32>;
> > +
> > +			out-ports {
> > +				port {
> > +					ddr2_tpdm2_out: endpoint {
> > +						remote-endpoint = <&ddr2_tn_in9>;
> > +					};
> > +				};
> > +			};
> > +		};
> > +
> > +		tpdm@12411000 {
> > +			compatible = "qcom,coresight-tpdm", "arm,primecell";
> > +			reg = <0x0 0x12411000 0x0 0x1000>;
> > +
> > +			clocks = <&aoss_qmp>;
> > +			clock-names = "apb_pclk";
> > +			label = "tpdm_ddr3_llcc_3";
>
> GPT points out the labels should be ddr2_, not ddr3_ on these nodes

Confirmed should be ddr2_ .

Thanks,
Jie

> Konrad