Re: [PATCH net-next v2 2/2] net: phy: qcom: qca808x: Add regulator management
From: Mohd Ayaan Anwar
Date: Sat Oct 17 2026 - 04:12:33 EST
On Fri, Oct 16, 2026 at 05:17:20PM +0200, Andrew Lunn wrote:
> > I was going to share a text version of the power-up diagram given in
> > this PHY's datasheet. This might help.
> >
> > Power-Up Sequence
> >
> > 1. DVDD asserted
> > |
> > |<-------- 10 ms -------->| (required for external power)
> > |
> > 2. DVDD18 / AVDD18 asserted
> >
> > 3. VDD1P25 asserted
> > |
> > |<-------- 0.2 ms ------->| (required for LDO to settle)
> > |
> > 4. VDD_LDO asserted
> >
> > 5. AVDD asserted
> > |
> > |<--------- 2 ms -------->| (required for XTL to oscillate)
> > |
> > 6. Crystal 50 MHz starts oscillating
> >
> > 7. PAD reset deasserted
> > |
> > |<------- 10 ms --------->| (deglitch time)
> >
>
> Are these supposed to be staggered? Or can you turn them all on at
> once.
Its a confusing diagram but from what I gather: there's no delay
required between 1., 3., and 5. They are shown as partially overlapping.
This might be a better representation of the diagram:
DVDD ..../-------------------------------------------------
|<--------- 10 ms ----------->|
| (external power) |
DVDD18/AVDD18 ................................../-------------------
VDD1P25 ............../---------------------------------------
|<0.2 ms>|
| LDO settling
VDD_LDO ......................../-----------------------------
AVDD ......................../-----------------------------
|< 2 ms >|
| crystal startup
Crystal 50 MHz ........................................../\/\/\/\/\/
PAD reset ..................................................../---
|<10 ms>|
deglitch
>
> 23ms does seem like the worst case.
>
Yes, I thought that 23ms would be a safe value after looking at the diagram.
Ayaan