[PATCH 1/8] dt-bindings: interconnect: add Qualcomm MSM8998 NoC
From: Dmitry Baryshkov
Date: Mon Oct 19 2026 - 11:20:53 EST
The MSM8998 interconnect provider driver has no device tree schema, so
the provider nodes it binds to can neither be described nor validated.
Document the eight MSM8998 NoC devices. Unlike the older RPM
interconnect bindings, the bus clocks of these providers are RPM
resources handled by the driver itself, so only the interface clocks
appear in the device tree. The MMSS AHB NoC has no register range of
its own - it shares the register space of the MMSS NoC - and is
therefore described as a child of the latter.
Co-developed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>
---
.../bindings/interconnect/qcom,msm8998.yaml | 192 +++++++++++++++++++++
include/dt-bindings/interconnect/qcom,msm8998.h | 133 ++++++++++++++
2 files changed, 325 insertions(+)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998.yaml
new file mode 100644
index 000000000000..0a05dc620cfd
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998.yaml
@@ -0,0 +1,192 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,msm8998.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm MSM8998 Network-On-Chip interconnect
+
+maintainers:
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxxx>
+ - Konrad Dybcio <konradybcio@xxxxxxxxxx>
+
+description: |
+ The Qualcomm MSM8998 interconnect providers support adjusting the
+ bandwidth requirements between the various NoC fabrics.
+
+properties:
+ compatible:
+ enum:
+ - qcom,msm8998-a1noc
+ - qcom,msm8998-a2noc
+ - qcom,msm8998-bimc
+ - qcom,msm8998-cnoc
+ - qcom,msm8998-gnoc
+ - qcom,msm8998-mnoc
+ - qcom,msm8998-mnoc-ahb
+ - qcom,msm8998-snoc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+allOf:
+ - $ref: qcom,rpm-common.yaml#
+ - if:
+ properties:
+ compatible:
+ const: qcom,msm8998-a1noc
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Aggregate1 NoC UFS AXI Clock
+ - description: UFS AXI Clock
+ - description: Aggregate1 NoC USB3 AXI Clock
+ - description: BLSP2 AHB Clock
+
+ clock-names:
+ items:
+ - const: aggre1_ufs_axi
+ - const: ufs_axi
+ - const: usb_axi
+ - const: blsp2_ahb
+
+ - if:
+ properties:
+ compatible:
+ const: qcom,msm8998-a2noc
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: SDCC2 AHB Clock
+ - description: SDCC4 AHB Clock
+ - description: BLSP1 AHB Clock
+ - description: IPA Clock
+
+ clock-names:
+ items:
+ - const: sdcc2_ahb
+ - const: sdcc4_ahb
+ - const: blsp1_ahb
+ - const: ipa
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,msm8998-cnoc
+ - qcom,msm8998-snoc
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: CPU-NoC High-performance Bus Clock
+
+ clock-names:
+ const: iface
+
+ - if:
+ properties:
+ compatible:
+ const: qcom,msm8998-mnoc
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: CPU-NoC High-performance Bus Clock
+ - description: MMSS NoC AXI Clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: mnoc_bus
+
+ interconnect-mnoc-ahb:
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: qcom,msm8998-mnoc-ahb
+
+ - if:
+ properties:
+ compatible:
+ const: qcom,msm8998-mnoc-ahb
+
+ then:
+ description:
+ The MMSS AHB NoC shares its register space with the MMSS NoC, so it is
+ described as a child of the latter and has no register range of its own.
+
+ properties:
+ clocks:
+ items:
+ - description: MMSS AHB Clock
+
+ clock-names:
+ const: bus
+
+ required:
+ - clocks
+ - clock-names
+
+ else:
+ required:
+ - reg
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,msm8998-bimc
+ - qcom,msm8998-gnoc
+
+ then:
+ properties:
+ clocks: false
+ clock-names: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-msm8998.h>
+ #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
+
+ interconnect@1008300 {
+ compatible = "qcom,msm8998-bimc";
+ reg = <0x01008300 0x77d00>;
+ #interconnect-cells = <2>;
+ };
+
+ interconnect@1740000 {
+ compatible = "qcom,msm8998-mnoc";
+ reg = <0x01740000 0x10000>;
+ clocks = <&mmcc MNOC_AHB_CLK>, <&mmcc MNOC_MAXI_CLK>;
+ clock-names = "iface", "mnoc_bus";
+ #interconnect-cells = <2>;
+
+ interconnect-mnoc-ahb {
+ compatible = "qcom,msm8998-mnoc-ahb";
+ clocks = <&mmcc AHB_CLK_SRC>;
+ clock-names = "bus";
+ #interconnect-cells = <2>;
+ };
+ };
diff --git a/include/dt-bindings/interconnect/qcom,msm8998.h b/include/dt-bindings/interconnect/qcom,msm8998.h
new file mode 100644
index 000000000000..3eb571e65554
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,msm8998.h
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxx>
+ * Copyright (c) 2022, Linaro Limited
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8998_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8998_H
+
+/* A1NOC */
+#define MASTER_PCIE_0 0
+#define MASTER_USB3 1
+#define MASTER_UFS 2
+#define MASTER_BLSP_2 3
+#define SLAVE_A1NOC_SNOC 4
+
+/* A2NOC */
+#define MASTER_IPA 0
+#define MASTER_CNOC_A2NOC 1
+#define MASTER_SDCC_2 2
+#define MASTER_SDCC_4 3
+#define MASTER_TSIF 4
+#define MASTER_BLSP_1 5
+#define MASTER_CRVIRT_A2NOC 6
+#define MASTER_CRYPTO_C0 7
+#define SLAVE_A2NOC_SNOC 8
+#define SLAVE_CRVIRT_A2NOC 9
+
+/* BIMC */
+#define MASTER_GNOC_BIMC 0
+#define MASTER_OXILI 1
+#define MASTER_MNOC_BIMC 2
+#define MASTER_SNOC_BIMC 3
+#define SLAVE_EBI 4
+#define SLAVE_HMSS_L3 5
+#define SLAVE_BIMC_SNOC_0 6
+#define SLAVE_BIMC_SNOC_1 7
+
+/* CNOC */
+#define MASTER_SNOC_CNOC 0
+#define MASTER_QDSS_DAP 1
+#define SLAVE_CNOC_A2NOC 2
+#define SLAVE_SSC_CFG 3
+#define SLAVE_MPM 4
+#define SLAVE_PMIC_ARB 5
+#define SLAVE_TLMM_NORTH 6
+#define SLAVE_PIMEM_CFG 7
+#define SLAVE_IMEM_CFG 8
+#define SLAVE_MESSAGE_RAM 9
+#define SLAVE_SKL 10
+#define SLAVE_BIMC_CFG 11
+#define SLAVE_PRNG 12
+#define SLAVE_A2NOC_CFG 13
+#define SLAVE_IPA 14
+#define SLAVE_TCSR 15
+#define SLAVE_SNOC_CFG 16
+#define SLAVE_CLK_CTL 17
+#define SLAVE_GLM 18
+#define SLAVE_SPDM 19
+#define SLAVE_GPUSS_CFG 20
+#define SLAVE_CNOC_MNOC_CFG 21
+#define SLAVE_QM_CFG 22
+#define SLAVE_MSS_CFG 23
+#define SLAVE_UFS_CFG 24
+#define SLAVE_TLMM_WEST 25
+#define SLAVE_A1NOC_CFG 26
+#define SLAVE_AHB2PHY 27
+#define SLAVE_BLSP_2 28
+#define SLAVE_PDM 29
+#define SLAVE_USB3_0 30
+#define SLAVE_A1NOC_SMMU_CFG 31
+#define SLAVE_BLSP_1 32
+#define SLAVE_SDCC_2 33
+#define SLAVE_SDCC_4 34
+#define SLAVE_TSIF 35
+#define SLAVE_QDSS_CFG 36
+#define SLAVE_TLMM_EAST 37
+#define SLAVE_CNOC_MNOC_MMSS_CFG 38
+#define SLAVE_SRVC_CNOC 39
+
+/* GNOC */
+#define MASTER_APSS_PROC 0
+#define SLAVE_GNOC_BIMC 1
+
+/* MNOC */
+#define MASTER_CNOC_MNOC_CFG 0
+#define MASTER_CPP 1
+#define MASTER_JPEG 2
+#define MASTER_MDP_P0 3
+#define MASTER_MDP_P1 4
+#define MASTER_ROTATOR 5
+#define MASTER_VENUS 6
+#define MASTER_VFE 7
+#define MASTER_VENUS_VMEM 8
+#define SLAVE_MNOC_BIMC 9
+#define SLAVE_VMEM 10
+#define SLAVE_SRVC_MNOC 11
+
+/* MNOC_AHB */
+#define MASTER_CNOC_MNOC_MMSS_CFG 0
+#define SLAVE_CAMERA_CFG 1
+#define SLAVE_CAMERA_THROTTLE_CFG 2
+#define SLAVE_MISC_CFG 3
+#define SLAVE_VENUS_THROTTLE_CFG 4
+#define SLAVE_VENUS_CFG 5
+#define SLAVE_VMEM_CFG 6
+#define SLAVE_MMSS_CLK_XPU_CFG 7
+#define SLAVE_MMSS_CLK_CFG 8
+#define SLAVE_DISPLAY_CFG 9
+#define SLAVE_DISPLAY_THROTTLE_CFG 10
+#define SLAVE_SMMU_CFG 11
+
+/* SNOC */
+#define MASTER_HMSS 0
+#define MASTER_QDSS_BAM 1
+#define MASTER_SNOC_CFG 2
+#define MASTER_BIMC_SNOC_0 3
+#define MASTER_BIMC_SNOC_1 4
+#define MASTER_A1NOC_SNOC 5
+#define MASTER_A2NOC_SNOC 6
+#define MASTER_QDSS_ETR 7
+#define SLAVE_HMSS 8
+#define SLAVE_LPASS 9
+#define SLAVE_WLAN 10
+#define SLAVE_SNOC_BIMC 11
+#define SLAVE_SNOC_CNOC 12
+#define SLAVE_IMEM 13
+#define SLAVE_PIMEM 14
+#define SLAVE_QDSS_STM 15
+#define SLAVE_PCIE_0 16
+#define SLAVE_SRVC_SNOC 17
+
+#endif
--
2.47.3