[PATCH 3/3] clk: stm32mp13: add the SPI1 to SPI5 bus clocks

[Gabriel Fernandez]

Register the bus interface clocks of the SPI1 to SPI5 instances, with
the IDs added to the binding by the previous patch. They are needed by
the I2S driver, which handles the bus interface clock separately from
the kernel clock.

Each bus clock is a gate on the APB bus clock its peripheral is attached
to (pclk1 for SPI2/3, pclk2 for SPI1 and pclk6 for SPI4/5). It uses the
same RCC enable bit as the matching SPIx_K kernel clock, and the gate
enable counter makes sure the bit is only cleared once both clocks are
off. SPI4 and SPI5 are also subject to the RCC secure configuration,
like their kernel clocks.

Update the number of clocks of the provider to cover the new IDs.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@xxxxxxxxxxx>
---
 drivers/clk/stm32/clk-stm32mp13.c | 32 +++++++++++++++++++++++++++++++-
 1 file changed, 31 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c
index 76cede5e47bc..90c4bfe1b2c4 100644
--- a/drivers/clk/stm32/clk-stm32mp13.c
+++ b/drivers/clk/stm32/clk-stm32mp13.c
@@ -17,7 +17,7 @@
 #define RCC_CLR_OFFSET		0x4
 
 /* Number of clock identifiers of the binding: highest ID + 1 */
-#define STM32MP13_LAST_CLK	(SAI2 + 1)
+#define STM32MP13_LAST_CLK	(SPI5 + 1)
 
 /* STM32 Gates definition */
 enum enum_gate_cfg {
@@ -717,6 +717,16 @@ static struct clk_stm32_gate tim17_k = {
 };
 
 /* Peripheral clocks */
+static struct clk_stm32_gate spi2 = {
+	.gate_id = GATE_SPI2,
+	.hw.init = CLK_HW_INIT("spi2", "pclk1", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate spi3 = {
+	.gate_id = GATE_SPI3,
+	.hw.init = CLK_HW_INIT("spi3", "pclk1", &clk_stm32_gate_ops, 0),
+};
+
 static struct clk_stm32_gate sai1 = {
 	.gate_id = GATE_SAI1,
 	.hw.init = CLK_HW_INIT("sai1", "pclk2", &clk_stm32_gate_ops, 0),
@@ -727,6 +737,11 @@ static struct clk_stm32_gate sai2 = {
 	.hw.init = CLK_HW_INIT("sai2", "pclk2", &clk_stm32_gate_ops, 0),
 };
 
+static struct clk_stm32_gate spi1 = {
+	.gate_id = GATE_SPI1,
+	.hw.init = CLK_HW_INIT("spi1", "pclk2", &clk_stm32_gate_ops, 0),
+};
+
 static struct clk_stm32_gate syscfg = {
 	.gate_id = GATE_SYSCFG,
 	.hw.init = CLK_HW_INIT("syscfg", "pclk3", &clk_stm32_gate_ops, 0),
@@ -832,6 +847,16 @@ static struct clk_stm32_gate bsec = {
 	.hw.init = CLK_HW_INIT("bsec", "pclk5", &clk_stm32_gate_ops, 0),
 };
 
+static struct clk_stm32_gate spi4 = {
+	.gate_id = GATE_SPI4,
+	.hw.init = CLK_HW_INIT("spi4", "pclk6", &clk_stm32_gate_ops, 0),
+};
+
+static struct clk_stm32_gate spi5 = {
+	.gate_id = GATE_SPI5,
+	.hw.init = CLK_HW_INIT("spi5", "pclk6", &clk_stm32_gate_ops, 0),
+};
+
 static struct clk_stm32_gate dma1 = {
 	.gate_id = GATE_DMA1,
 	.hw.init = CLK_HW_INIT("dma1", "ck_mlahb", &clk_stm32_gate_ops, 0),
@@ -1356,6 +1381,9 @@ static const struct clock_config stm32mp13_clock_cfg[] = {
 	STM32_GATE_CFG(TIM17_K, tim17_k, SECF_TIM17),
 
 	/* Peripheral clocks */
+	STM32_GATE_CFG(SPI1, spi1, SECF_NONE),
+	STM32_GATE_CFG(SPI2, spi2, SECF_NONE),
+	STM32_GATE_CFG(SPI3, spi3, SECF_NONE),
 	STM32_GATE_CFG(SAI1, sai1, SECF_NONE),
 	STM32_GATE_CFG(SAI2, sai2, SECF_NONE),
 	STM32_GATE_CFG(SYSCFG, syscfg, SECF_NONE),
@@ -1368,6 +1396,8 @@ static const struct clock_config stm32mp13_clock_cfg[] = {
 	STM32_GATE_CFG(TZPC, tzpc, SECF_TZC),
 	STM32_GATE_CFG(IWDG1, iwdg1, SECF_IWDG1),
 	STM32_GATE_CFG(BSEC, bsec, SECF_BSEC),
+	STM32_GATE_CFG(SPI4, spi4, SECF_SPI4),
+	STM32_GATE_CFG(SPI5, spi5, SECF_SPI5),
 	STM32_GATE_CFG(DMA1, dma1, SECF_NONE),
 	STM32_GATE_CFG(DMA2, dma2, SECF_NONE),
 	STM32_GATE_CFG(DMAMUX1, dmamux1, SECF_NONE),

-- 
2.43.0