Re: [PATCH] dt-bindings: cpufreq: qcom-nvmem: Allow generic OPP tables
From: Varadarajan Narayanan
Date: Wed Oct 21 2026 - 04:51:42 EST
On Wed, Oct 21, 2026 at 02:10:10PM +0530, Varadarajan Narayanan wrote:
> On Wed, Oct 21, 2026 at 08:17:36AM +0200, Krzysztof Kozlowski wrote:
> > On 21/10/2026 07:38, Varadarajan Narayanan wrote:
> > > On Sat, Oct 17, 2026 at 06:45:53PM +0200, Krzysztof Kozlowski wrote:
> > >> On Thu, Oct 15, 2026 at 04:25:28PM +0530, Varadarajan Narayanan wrote:
> > >>> The OPP table node-name pattern also matches peripheral OPP tables on
> > >>> supported SoCs. However, it only handles Qualcomm CPU and level OPP
> > >>> compatibles, causing unevaluatedProperties errors for generic
> > >>> operating-points-v2 tables.
> > >>
> > >> But the select should not select them. How can I reproduce the issue?
> > >
> > > Sorry for the delay, it was a long weekend here.
> > >
> > > With the attached patch, I get the following error.
> > >
> > Does not apply,
>
> Sorry. Have rebased to next-20261020 and attached, please see.
>
> > but exactly that sort of opp-table is already all over the tree. Just
> > check yourself.
>
> From what I see, SoCs that don't use operating-points-v2-kryo-cpu for the
> CPU's opp table don't face an issue. Since ipq5210's CPU opp table's
> compatible is operating-points-v2-kryo-cpu, it is facing this unevaluated
> properties error.
>
> The qcom-cpufreq-nvmem.yaml change is approved in [1]. And the change to
> ipq5210.dtsi is to address the feedback in [2].
>
> Thanks
> Varada
>
> 1 - https://lore.kernel.org/linux-arm-msm/20260703-lively-intelligent-raptor-5edfbf@quoll/
> 2 - https://lore.kernel.org/linux-arm-msm/06e6868a-c106-40b1-85fb-5ebbc01eff16@xxxxxxxxxxxxxxxx/
Forgot the attachment... Added now.
diff --git a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml
index 547265b8b118..2f5dbb59034c 100644
--- a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml
+++ b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml
@@ -27,6 +27,7 @@ select:
enum:
- qcom,apq8064
- qcom,apq8096
+ - qcom,ipq5210
- qcom,ipq5332
- qcom,ipq6018
- qcom,ipq8064
diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
index 2cdc10529c48..b8172f6f1030 100644
--- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
@@ -84,6 +84,14 @@ memory@80000000 {
reg = <0x0 0x80000000 0x0 0x0>;
};
+ i2c_opp_table_32mhz: opp-table-qup32mhz {
+ compatible = "operating-points-v2";
+
+ opp-32000000 {
+ opp-hz = /bits/ 64 <32000000>;
+ };
+ };
+
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
@@ -179,6 +187,45 @@ uart1: serial@1a84000 {
status = "disabled";
};
+
+ i2c0: i2c@1a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01a88000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_QUPV3_WRAP_SE2_CLK>;
+ clock-names = "se";
+ clock-frequency = <400000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ operating-points-v2 = <&i2c_opp_table_32mhz>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@1a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01a8c000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_QUPV3_WRAP_SE3_CLK>;
+ clock-names = "se";
+ clock-frequency = <400000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ operating-points-v2 = <&i2c_opp_table_32mhz>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@1a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01a94000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_QUPV3_WRAP_SE5_CLK>;
+ clock-names = "se";
+ clock-frequency = <400000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ operating-points-v2 = <&i2c_opp_table_32mhz>;
+ status = "disabled";
+ };
};
sdhc: mmc@7804000 {