[PATCH 3/5] spi: tegra114: Assert CS between transfers when cs_change is set

[Vishwaroop A]

A spi_message may set cs_change on a non-final transfer to toggle CS
before the next transfer of the same message. The driver deasserts
CS in tegra_spi_transfer_end() and, until now, never drove it active
again, so the following transfer in the same message ran with CS
inactive and clients received garbage.

After ending the current transfer, run the CS-off gap through
spi_transfer_cs_change_delay_exec() so that the core's default
minimum applies when the client leaves cs_change_delay unset, then
reassert CS for the following transfer for both GPIO CS and native
software CS.

Fixes: f4fade12d506 ("spi/tegra114: Correct support for cs_change")
Signed-off-by: Vishwaroop A <va@xxxxxxxxxx>
---
 drivers/spi/spi-tegra114.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index d1118f1f2cb3..bd7b13c7f5df 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -1110,6 +1110,17 @@ static int tegra_spi_transfer_one_message(struct spi_controller *host,
 		} else if (xfer->cs_change) {
 			spi_transfer_delay_exec(xfer);
 			tegra_spi_transfer_end(spi);
+			spi_transfer_cs_change_delay_exec(msg, xfer);
+			if (spi_get_csgpiod(spi, 0))
+				gpiod_set_value(spi_get_csgpiod(spi, 0), 1);
+			if (!tspi->use_hw_based_cs) {
+				if (spi->mode & SPI_CS_HIGH)
+					tspi->command1_reg |= SPI_CS_SW_VAL;
+				else
+					tspi->command1_reg &= ~SPI_CS_SW_VAL;
+				tegra_spi_writel(tspi, tspi->command1_reg,
+						 SPI_COMMAND1);
+			}
 		}
 
 	}
-- 
2.17.1