Re: [PATCH v6 00/18] x86,fs/resctrl: Add kernel-mode (e.g., PLZA) support to the resctrl subsystem
From: Babu Moger
Date: Wed Oct 21 2026 - 14:46:04 EST
Hi Drew, Yunhui,
On 10/16/26 19:13, Drew Fustini wrote:
On Thu, Oct 01, 2026 at 10:10:23AM -0500, Babu Moger wrote:That's great to hear. Please feel free to share any feedback or suggestions that would make this easier for RISC-V.
Hi All,
This series adds support for AMD's Privilege-Level Zero Association
(PLZA) so kernel work can use a separate resource allocation and/or
monitoring association from the user task, and wires it up through a
small generic "kernel mode" (kmode) layer in fs/resctrl so future
architectures can plug in without touching (hopefully) core resctrl.
Hi Babu,
Yunhui Cui (cc'd) recently proposed a RISC-V extension [1] with similar
functionality. It adds a new CSR with a RCID (like CLOSID) and MCID
(like RMID) to use when the cpu switches to the privilege level that the
kernel runs in (supervisor-mode in RISC-V terminology). The srmcfg_assoc
register is defined as:
Bits Field
-------- --------
11:0 RCID
12 RCID_EN
15:13 Reserved
27:16 MCID
28 MCID_EN
30:29 Reserved
31 ASSOC_EN
It is similar enough to PLZA that I believe that this series could work
for RISC-V. Hopefully Yunhui Cui can comment further.
Thanks,
Babu