Re: [PATCH v3 0/4] sparc64: D-cache alias flushing fixes

[Stian Halseth]

Hi Imre,

On Thu, 2026-10-22 at 01:33 +0200, Imre Kaloz wrote:
> These fix D-cache alias flushing on sparc64 CPUs with a virtually
> indexed L1 D-cache (Spitfire and Cheetah).
> 

Tested on top of Andreas' for-next on my V240 (sun4u, 2xUltraSPARC
IIIi), against the same for-next without the series, both with THP
enabled. The stale reads through a reused vmalloc address are gone, and
moving an 8 MB THP to the other colour now takes milliseconds instead
of seven seconds.

I also checked 1/4 on its own by booting with the vmemmap check in 3/4
disabled. The four cross calls from sparse_init() still reach
xcall_deliver(), but physical address 0 is now left untouched.

4/4 can't really be tested on sparc64, since move_ptes() never
batches, but it builds and nothing changes. Each patch builds
cleanly for SMP and UP.

Tested-by: Stian Halseth <stian@xxxxxx> # Sun Fire V240

/Stian

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