Re: [PATCH 14/18] riscv: dts: zhihe: add A210 UARTs

[Philipp Zabel]

On Do, 2026-10-22 at 03:53 +0800, Han Gao via B4 Relay wrote:
> From: Zhiguo Zhu <zhiguo.zhu@xxxxxxxxxxxxxxxxx>
> 
> Add the ten A210 UARTs with their clocks, resets and interrupts, using
> the snps,dw-apb-uart compatible.
> 
> Signed-off-by: Zhiguo Zhu <zhiguo.zhu@xxxxxxxxxxxxxxxxx>
> Co-developed-by: Han Gao <gaohan@xxxxxxxxxxx>
> Signed-off-by: Han Gao <gaohan@xxxxxxxxxxx>
> ---
>  arch/riscv/boot/dts/zhihe/a210.dtsi | 150 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 150 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/zhihe/a210.dtsi b/arch/riscv/boot/dts/zhihe/a210.dtsi
> index bbad51a3edb0..a07b67d10633 100644
> --- a/arch/riscv/boot/dts/zhihe/a210.dtsi
> +++ b/arch/riscv/boot/dts/zhihe/a210.dtsi
> @@ -405,6 +405,66 @@ rst_peri1: reset-controller@2010400 {
>  			#reset-cells = <1>;
>  		};
>  
> +		uart0: serial@2014000 {
> +			compatible = "snps,dw-apb-uart";

Prepend a vendor compatible if you need two resets, similar to
"starfive,jh7100-uart"?

> +			reg = <0x0 0x02014000 0x0 0x400>;
> +			clocks = <&clk_peri PERI1_UART0_SCLK_EN>,
> +				 <&clk_peri PERI1_UART0_PCLK_EN>;
> +			clock-names = "baudclk", "apb_pclk";
> +			interrupt-parent = <&intc>;
> +			interrupts = <321 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			resets = <&rst_peri1 PERI1_UART0_PRST>;

This looks to me like it should be

			resets = <&rst_peri1 PERI1_UART0_PRST>,
				 <&rst_peri1 PERI1_UART0_S_RST>;

instead.

regards
Philipp