Re: [PATCH 5/6] arm64: dts: qcom: kodiak: use thermal hw-bin trips

From: Gaurav Kohli

Date: Thu Oct 22 2026 - 09:44:56 EST




On 10/22/2026 2:39 PM, Konrad Dybcio wrote:
On 10/2/26 12:47 PM, Gaurav Kohli wrote:
From: Amit Kucheria <amit.kucheria@xxxxxxxxxxxxxxxx>

kodiak-based SoCs are binned at manufacturing time, with the bin
computed from the jtag-id and feat-id qfprom fuses. The tsens driver
now reads these and feeds the resulting bin to the thermal core, which
selects per-bin trip temperatures.

Add the jtag-id and feat-id nvmem cells to the tsens nodes and convert
the passive mitigation trip points from a fixed 95C to per-bin values
(95C for bin 0x1, 105C for bin 0x2) using the new
temperature-bin/thermal-hw-bin properties.

Signed-off-by: Amit Kucheria <amit.kucheria@xxxxxxxxxxxxxxxx>
Co-developed-by: Gaurav Kohli <gaurav.kohli@xxxxxxxxxxxxxxxx>
Signed-off-by: Gaurav Kohli <gaurav.kohli@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 56 +++++++++++++++++++++++++++---------
1 file changed, 42 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 347815e5983e..f3bb9cd8f393 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -1019,6 +1019,16 @@ gpu_speed_bin: gpu-speed-bin@1e9 {
reg = <0x1e9 0x2>;
bits = <5 8>;
};
+ jtag_id: jtag-id@180 {
+ reg = <0x180 0x4>;
+ /* bits = <offset width>: 20 bits at offset 0 */
+ bits = <0 20>;
+ };
+ feat_id: feat-id@180 {
+ reg = <0x180 0x4>;
+ /* bits = <offset width>: 8 bits at offset 20 */
+ bits = <20 8>;
+ };

Couple nits: please keep a \n between each subnode

thanks for review, will fix this in v2.



[...]

cpu0_alert1: trip-point1 {
- temperature = <95000>;
+ temperature-bin = <95000 105000>;

Please do <foo>, <bar> instead of <foo bar>

Sure, will update.


Konrad