Re: [PATCH v2 1/2] arm64: dts: imx8qm-mek: Re-enable A72 cluster after ERR050104 workaround

[Alexander Stein]

Hi Peng,

Am Freitag, 23. Oktober 2026, 04:56:59 Mitteleuropäische Sommerzeit schrieb Peng Fan (OSS):
> From: Peng Fan <peng.fan@xxxxxxx>
> 
> The ERR050104 cache coherency workaround for i.MX8QM/8QP has been
> merged upstream (d44e08dab27d). The workaround addresses the incorrect
> wiring of upper address bits in the A53 subsystem that corrupts TLBI and
> IC maintenance operations between A53 and A72 clusters.
> 
> Previously the A72 CPUs (cpu@100, cpu@101), the cpu-map, and the
> cpu1-thermal zone were removed from the MEK board DT to avoid incorrect
> cross-cluster coherency maintenance. With the software workaround in
> place, restore all deleted nodes and add A72_0/A72_1 to the PMIC thermal
> cooling-device map so both clusters are properly managed.
> 
> Signed-off-by: Peng Fan <peng.fan@xxxxxxx>

Maybe it's woth mentioning you are essentially also reverting commit
bce07345481cd ("arm64: dts: imx8qm-mek: delete A72 thermal zone").

But either way:
Reviewed-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx>

Best regards
Alexander

> ---
>  arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 14 +++-----------
>  1 file changed, 3 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> index 9e49ac377162b..d346958965026 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> @@ -17,16 +17,6 @@ chosen {
>  		stdout-path = &lpuart0;
>  	};
>  
> -	cpus {
> -		/delete-node/ cpu-map;
> -		/delete-node/ cpu@100;
> -		/delete-node/ cpu@101;
> -	};
> -
> -	thermal-zones {
> -		/delete-node/ cpu1-thermal;
> -	};
> -
>  	memory@80000000 {
>  		device_type = "memory";
>  		reg = <0x00000000 0x80000000 0 0x40000000>;
> @@ -995,7 +985,9 @@ map0 {
>  				cooling-device = <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>  						 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>  						 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> -						 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +						 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +						 <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +						 <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>  			};
>  		};
>  	};
> 
> 


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