Re: [PATCH 1/8] i3c: renesas: Fix zero I2C SCL rate on pure I3C buses

[Diogo Ivo]

On 10/23/2026 11:27 AM, Wolfram Sang wrote:
> On Tue, Oct 20, 2026 at 10:14:55AM +0100, Diogo Ivo wrote:
> > On a pure I3C bus there are no I2C devices, so the I3C core leaves
> > bus->scl_rate.i2c at zero if i2c-scl-hz is not specified in DT.
> > Deriving i2c_total_ticks from that zero rate programs a zero-width
> > open-drain SCL into the STDBR open-drain fields, which are still used
> > in pure I3C mode for example in DAA.
> >
> > Fall back to the 1 MHz FM+ limit instead, the fastest rate an I2C
> > device could have, so that a sane open-drain timing is programmed.
> >
> > Fixes: d028219a9f14 ("i3c: master: Add basic driver for the Renesas I3C controller")
> > Cc: stable@xxxxxxxxxxxxxxx
> > Signed-off-by: Diogo Ivo <diogo.ivo.sx@xxxxxxxxxxx>
>
> Great catch! Kudos for adding a good comment. I agree with Geert about
> using the ternary operator, though. After that, you can add my:
>
> Reviewed-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>

Ok, will do.

Thanks,
Diogo