Re: [PATCH v4 4/5] drm/msm/adreno: Add Adreno 620

[Konrad Dybcio]

On 10/27/26 8:14 AM, Ishu Brar via B4 Relay wrote:
> From: Ishu Brar <patches@xxxxxxx>
> 
> Add the catalog entry for the Adreno 620 (chip id 0x06020000) found in
> the Snapdragon 765/765G/768G (SM7250). It is an A650 derivative and
> uses its SQE and GMU firmware and protect table, together with the A620
> zap shader.
> 
> The speed-bin fuse values map to the OPP bins as in the downstream
> "lito" devicetree: fuse 0 is the default bin and fuse 132 and 115 are
> the two alternate ones.
> 
> The GMU clock gating mode is 0x00020202, which is what the downstream
> driver programs on every A6xx except the A612 and A615 family. Use the
> shared list of Bus Clock Managers so that the GMU bandwidth table is
> generated from the bandwidth levels of the GPU OPP table.
> 
> Signed-off-by: Ishu Brar <patches@xxxxxxx>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>

Konrad