Re: [PATCH v2 14/16] KVM: x86/pmu: Ignore AnyThread bit if CPUID.0AH:EDX[15] is set

[Chen, Zide]

On 10/28/2026 4:50 PM, Jim Mattson wrote:
> On Thu, Aug 27, 2026 at 3:48 PM Zide Chen <zide.chen@xxxxxxxxx> wrote:
>>
>> Intel PerfMon v5 introduces the ANYTHREAD_DEPRECATION capability
>> (CPUID.0AH:EDX[15]) to indicate that AnyThread counting is deprecated
>> and that writes to the AnyThread bit in IA32_PERFEVTSELx are ignored.
>>
>> When ANYTHREAD_DEPRECATION is present in the guest CPUID, emulate the
>> architectural behavior and silently ignore writes to the AnyThread bit
>> instead of injecting #GP.
>>
>> Continue to inject #GP when ANYTHREAD_DEPRECATION is not present in the
>> guest CPUID, e.g. for PerfMon v3/v4 guests or when the capability is
>> not configured for a PerfMon v5+ guest.
>>
>> Advertise CPUID.0AH:EDX[15] only for PMU version 5+ guests, since the
>> bit doesn't exist below version 5.
>>
>> Signed-off-by: Zide Chen <zide.chen@xxxxxxxxx>
>> ---
>> v2:
>> - Advertise anythread_deprecated only if kvm_pmu_cap.version >= 5.
>> - Add the missing AnyThr bit handling for IA32_FIXED_CTR_CTRL.
>> - Update the comments to be clearer.
>> ---
>>  arch/x86/kvm/cpuid.c         |  2 +-
>>  arch/x86/kvm/vmx/pmu_intel.c | 19 +++++++++++++++++++
>>  2 files changed, 20 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
>> index 63201d4ea4a1..ef208906b3ee 100644
>> --- a/arch/x86/kvm/cpuid.c
>> +++ b/arch/x86/kvm/cpuid.c
>> @@ -1542,7 +1542,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
>>                                             KVM_MAX_NR_FIXED_COUNTERS);
>>                 edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed;
>>
>> -               if (kvm_pmu_cap.version)
>> +               if (kvm_pmu_cap.version >= 5)
>>                         edx.split.anythread_deprecated = 1;
>>
>>                 entry->eax = eax.full;
>> diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
>> index c7472778137a..599c69dfa6e3 100644
>> --- a/arch/x86/kvm/vmx/pmu_intel.c
>> +++ b/arch/x86/kvm/vmx/pmu_intel.c
>> @@ -446,6 +446,12 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>>                 if (data & pmu->fixed_ctr_ctrl_rsvd)
>>                         return 1;
>>
>> +               /*
>> +                * This is to emulate ANYTHREAD_DEPRECATION. Guests without
>> +                * support for it would have had the write rejected by
>> +                * pmu->fixed_ctr_ctrl_rsvd above.
>> +                */
>> +               data &= ~intel_pmu_fixed_ctrl_bits(pmu, INTEL_FIXED_0_ANYTHREAD);
>>                 if (pmu->fixed_ctr_ctrl != data)
>>                         reprogram_fixed_counters(pmu, data);
>>                 break;
>> @@ -494,6 +500,8 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>>                         if (data & eventsel_rsvd)
>>                                 return 1;
>>
>> +                       /* See above comments for MSR_CORE_PERF_FIXED_CTR_CTRL. */
>> +                       data &= ~ARCH_PERFMON_EVENTSEL_ANY;
>>                         if (data != pmc->eventsel) {
>>                                 pmc->eventsel = data;
>>                                 pmc->eventsel_hw = data;
>> @@ -603,6 +611,17 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
>>         pmu->pmc_exists64 = (BIT_ULL(nr_gp_counters) - 1) &
>>                             kvm_pmu_cap.cntr_mask64;
>>
>> +       /*
>> +        * AnyThread counting is not supported by KVM due to cross-VM
>> +        * information leakage concerns on SMT cores. Therefore, AnyThread
>> +        * remains unavailable for PerfMon v3/v4 guests, where AnyThread
>> +        * deprecation is not enumerated.
>> +        */
>> +       if (pmu->version >= 5 && edx.split.anythread_deprecated) {
>> +               pmu->eventsel_rsvd &= ~ARCH_PERFMON_EVENTSEL_ANY;
>> +               fixed_enable_bits |= INTEL_FIXED_0_ANYTHREAD;
>> +       }
>> +
> 
> According to Intel SDM Vol. 4, Table 2-2 ("IA-32 Architectural MSRs"), only
> Fixed Counters 0, 1, and 2 have an AnyThread bit (bits 2, 6, and 10 of
> IA32_FIXED_CTR_CTRL). FC3 has never had an AnyThread bit;
> IA32_FIXED_CTR_CTR[bit 14] is reserved in PerfMon v5 and becomes
> METRICS_CLEAR_EN in PerfMon v6. Passing INTEL_FIXED_0_ANYTHREAD to
> intel_pmu_fixed_ctrl_bits() will wrongly clear bit 14 in
> pmu->fixed_ctr_ctrl_rsvd once Fixed Counter 3 is enabled.

Right, the IA32_FIXED_CTR_CTR[bit 14] should be handled differently.
Thanks!
> On hardware with CPUID.0AH:EDX.ANYTHREAD_DEPRECATION[15] = 1, if software
> sets the AnyThread bit in IA32_PERFEVTSELx or IA32_FIXED_CTR_CTRL and then
> reads the MSR back with RDMSR, does hardware return 0 for the AnyThread
> bit, or does it return 1 but otherwise ignore the bit?

It returns 1. That said, the current implementation, which clears the
AnyThread bit in intel_pmu_set_msr(), breaks this behavior.

To make matters more subtle, in the case of an invalid configuration
where ANYTHREAD_DEPRECATION is set in the guest CPUID while deprecation
is not supported by the host (Ice Lake, for instance), it is better for
KVM not to pass the AnyThread bits to the host hardware and expect them
to be ignored by the host.

Is the complete solution to keep the AnyThread bits set in the
guest-visible states (pmc->eventsel and pmu->fixed_ctr_ctrl) for RDMSR
readback, but drop them from the hardware-visible states (their _hw
counterparts)?