[PATCH 0/2] Renesas RZ/G3E DSI/LVDS clk improvements

[Tommaso Merciai]

Dear All,

This patch series improves the handling of the PLLDSI mux on the RZ/G3E
SoC, which selects between the LVDS path, a fixed division by 7, and the
DSI/RGB path, a programmable divider.

PATCH 1/2: Forward PLLDSI mux rate requests to the parent via
clk_mux_ops.determine_rate(). Drop struct rzv2h_plldsi_mux_clk.

PATCH 2/2: Moves the 4/7 duty cycle of the LVDS path from the mux to the
divider that produces it, similar to the work done on RZ/G3L [1] .

[1] https://lore.kernel.org/all/20260811182729.360959-1-biju.das.jz@xxxxxxxxxxxxxx/

Kind regards,
Tommaso

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx>
---
Tommaso Merciai (2):
      clk: renesas: rzv2h: Forward PLLDSI mux rate requests to the parent
      clk: renesas: rzv2h: Report the DSI duty cycle from the LVDS divider

 drivers/clk/renesas/r9a09g047-cpg.c |   4 +-
 drivers/clk/renesas/rzv2h-cpg.c     | 195 ++++++++++++++++++------------------
 drivers/clk/renesas/rzv2h-cpg.h     |   6 +-
 3 files changed, 107 insertions(+), 98 deletions(-)
---
base-commit: b427a7529bc420a22cb22ea09cc788e925804e8e
change-id: 20261029-tm-ssgrlpcsrc-2083-v5-clk-duty-fixes-c009586b76c8

Best regards,
--  
Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx>