Re: [PATCH v4 1/3] dt-bindings: edac: xlnx,versal-ddrmc: Add xlnx,versal-xilsem compatible

[Borislav Petkov]

On Thu, Oct 29, 2026 at 03:52:35PM +0100, Michal Simek wrote:
> Let me jump to it and start that discussion again

Sure, but pls trim your reply. I almost missed it from the gazillion pages of
quoted text.

> Please correct me if I am wrong but today edac core only checks that there
> should be only one MC edac but there could be multiple EDAC devices.

An EDAC driver contains controls for all the RAS functionality in a platform.

> XILSEM edac device is present on Versal and Versal NET SOCs.
> https://docs.amd.com/r/en-US/oslib_rm/Tool-Configuration-for-XilSEM
> (Actually also on Versal Gen 2 but firmware interface is going to be different).
> 
> I don't think we should try to integrate EDAC memory controller with EDAC
> device because their usage is independent of each other.

Are you saying that you will have this XILSEM hw in different platforms?

IOW, you will have a Versal or Versalnet thing and then something else, and
then XILSEM will be in all of them?

Then perhaps it is better to have it as a separate EDAC "driver". In air
quotes because this is not really a driver but simply a wrapper so that it can
be called an EDAC driver.

It all depends on what hw configurations will be built.

But if you have XILSEM *only* with Versal, then I don't want a separate EDAC,
hm, driver.

I don't want to maintain a zoo of "EDAC drivers", each for the RAS
functionality in a hw functional unit. IOW, I don't want to have:

AMD64_EDAC_L1
AMD64_EDAC_L2
AMD64_EDAC_L3
AMD64_EDAC_DRAM
AMD64_EDAC_SB
...

and whatever else hw blocks you can imagine which have RAS capability.

Makes sense?

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette