Re: [Patch v5 13/18] perf/x86/intel: Refresh LBR stack for non-PEBS LBR events if needed

[Peter Zijlstra]

On Fri, Oct 30, 2026 at 09:54:02AM +0800, Mi, Dapeng wrote:

> >> @@ -4012,8 +4023,14 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status)
> >>  
> >>  		perf_sample_data_init(&data, 0, last_period);
> >>  
> >> -		if (has_branch_stack(event))
> >> +		if (has_branch_stack(event)) {
> >> +			if (lbr_need_update) {
> >> +				intel_pmu_lbr_read(&cpuc->lbr_stack,
> >> +					cpuc->lbr_entries, cpuc->lbr_counters);
> >> +				lbr_need_update = false;
> >> +			}
> >>  			intel_pmu_lbr_save_brstack(&data, cpuc, event);
> >> +		}
> >>  
> >>  		x86_pmu_clear_perf_regs(regs);
> >>  		x86_pmu_update_perf_regs(event, &data, regs, false);

> > Or... you move intel_pmu_lbr_read() from handle_irq() into pmi_common()
> > after we done the PEBS things?
> 
> Yes, I ever tried to do that, but I found it would break the PEBS LBR
> sampling on the platforms prior to ICE LAKE. The PEBS doesn't support
> snapshot LBR stack on these old platforms, so PMI handler has to snapshot
> the LBR stack before draining the PEBS buffer.

Argh; we have so many variations :-(

Still, re-reading those MSRs seems wasteful, esp. if most modern chips
will be affected.

Can't we have a toggle between early and late LBR read or something?