Re: [PATCH 14/21] soundwire: amd: Preserve lane control bits in amd_sdw_port_enable()

[Lee Jones]

On Fri, 30 Oct 2026, Mukunda,Vijendar wrote:

> 
> 
> On 10/30/26 16:16, Lee Jones wrote:
> > [You don't often get email from lee@xxxxxxxxxx. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> > 
> > lane_ctrl_ch_en_reg holds both the channel enable mask
> > (AMD_DPN_CH_EN_CHMASK) and the lane control field
> > (AMD_DPN_CH_EN_LCTRL) programmed by amd_sdw_transport_params().  When
> > enable_ch->enable is false, amd_sdw_port_enable() writes 0 to the entire
> > register instead of clearing only AMD_DPN_CH_EN_CHMASK, wiping out the
> > configured lane control bits.
> > 
> > Clear only the AMD_DPN_CH_EN_CHMASK field when disabling port channels.
> 
> Multi-lane is not supported on any of the platforms handled by this
> function (ACP6.3, ACP7.0, ACP7.1, ACP7.2). AMD_DPN_CH_EN_LCTRL
> (bits [2:0]) is never programmed for these platforms, so it always
> reads back as 0. Writing 0 to the entire register is therefore
> functionally identical to clearing only AMD_DPN_CH_EN_CHMASK.
> 
> Upcoming AMD platforms use an entirely different implementation and
> will not use this code path either.
> 
> The described bug has no practical impact on any hardware this code
> runs on, so the Fixes: tag and Cc: stable@xxxxxxxxxxxxxxx are not
> warranted. Please drop this patch.

Thanks for the review.

Wilco.  I'll go manually turn down the Sashiko bug to this effect as well.

-- 
Lee Jones