[PATCH] ASoC: tas2770: Fix VISENSE at sample rates greater than 48 kHz

[James Calligeros]

On reset, TAS2770 is configured to both transmit and receive on the
falling edge of the I2S clock. At sample rates higher than 48 kHz,
this causes strange artefacts in any transmitted VISENSE data which
manifest as corrupted/nonsensical readings for voltage and current
once decoded. Transmitting on the rising edge of the clock instead
results in correct VISENSE data at all sample rates.

Unconditionally configure the codec to transmit data on the rising
edge of the I2S clock when setting up VISENSE transmit.

Fixes: 1a476abc723e ("tas2770: add tas2770 smart PA kernel driver")
Fixes: 6553ee024b44 ("ASoC: tas2770: Factor out set_ivsense_slots")
Signed-off-by: James Calligeros <jcalligeros99@xxxxxxxxx>
---
 sound/soc/codecs/tas2770.c | 9 +++++++++
 sound/soc/codecs/tas2770.h | 1 +
 2 files changed, 10 insertions(+)

diff --git a/sound/soc/codecs/tas2770.c b/sound/soc/codecs/tas2770.c
index 882e19857697..41e4fcf09c25 100644
--- a/sound/soc/codecs/tas2770.c
+++ b/sound/soc/codecs/tas2770.c
@@ -222,6 +222,15 @@ static int tas2770_set_ivsense_transmit(struct tas2770_priv *tas2770,
 	struct snd_soc_component *component = tas2770->component;
 	int ret;
 
+	/*
+	 * At sample rates >48 kHz, transmitting VISENSE on the same clock
+	 * edge as receiving seems to cause artefacts in the VISENSE data.
+	 * Send on the rising edge of the clock instead.
+	 */
+	ret = snd_soc_component_update_bits(component, TAS2770_TDM_CFG_REG4,
+					    TAS2770_TDM_CFG_REG4_TX_EDGE_FALLING,
+					    TAS2770_TDM_CFG_REG4_TX_EDGE_RISING);
+
 	ret = snd_soc_component_update_bits(component, TAS2770_TDM_CFG_REG5,
 					    TAS2770_TDM_CFG_REG5_VSNS_MASK |
 					    TAS2770_TDM_CFG_REG5_50_MASK,
diff --git a/sound/soc/codecs/tas2770.h b/sound/soc/codecs/tas2770.h
index 102040b6bdf8..45bbd75fb09d 100644
--- a/sound/soc/codecs/tas2770.h
+++ b/sound/soc/codecs/tas2770.h
@@ -75,6 +75,7 @@
 #define TAS2770_TDM_CFG_REG4_TX_FILL BIT(4)
 #define TAS2770_TDM_CFG_REG4_TX_OFFSET_MASK GENMASK(3, 1)
 #define TAS2770_TDM_CFG_REG4_TX_EDGE_FALLING BIT(0)
+#define TAS2770_TDM_CFG_REG4_TX_EDGE_RISING	0
     /* TDM Configuration Reg5 */
 #define TAS2770_TDM_CFG_REG5  TAS2770_REG(0X0, 0x0F)
 #define TAS2770_TDM_CFG_REG5_VSNS_MASK  BIT(6)

---
base-commit: 11ae63bd9030349a0136fb2edd1622a4a029edc8
change-id: 20261030-tas2770-sdout-clkedge-b4e39db82720

Best regards,
--  
James Calligeros <jcalligeros99@xxxxxxxxx>