[PATCH 05/12] cxiverbs: define the native direct-verbs resource interface

[Doug Ledford]

Add cxidv.h, the public direct verbs API of the provider.  The CXI
hardware has resources that verbs has no object for (services, LNIs,
communication profiles, event queues, command queues, counting events,
wait objects, CSR mappings and PIDs), and a privileged consumer such
as a workload manager or the libcxi library needs to provision and
use them explicitly.  This header defines those entry points and
their attribute structures.

The telemetry of the NIC is part of the interface.  cxidv_telem.h names
every telemetry item and the predefined item sets, and cxi_telem.c maps
names to items and sets, so a monitor reads telemetry with
ibv_read_counters_ex() and needs no per-file sysfs interface.

Ownership is explicit throughout: nothing is created as a side effect
of opening the device or allocating a PD.  An LNI is allocated against
a service, a PD is allocated from an LNI, and the device-wide PID is
bound to the PD.  Every cxidv_alloc_*() has a matching
cxidv_destroy_*().

The additions for retry-handler style consumers are privileged:
cxidv_map_csrs() and the checked cxidv_read_csr()/cxidv_write_csr()
accessors, event queues registered with the PCT, pollable wait
descriptors, target and restricted trigger command queues, counting
events with a caller supplied write-back page, and the administrative
inbound wait.  Each requires CAP_SYS_ADMIN in the kernel.

Co-developed-by: Iraimani P <iraimani.pavadai@xxxxxxx>
Signed-off-by: Iraimani P <iraimani.pavadai@xxxxxxx>
Signed-off-by: Doug Ledford <doug.ledford@xxxxxxx>
---
 providers/cxi/cxi_telem.c   | 3948 +++++++++++++++++++++++++++++++++++++++++++
 providers/cxi/cxidv.h       |  418 +++++
 providers/cxi/cxidv_telem.h | 1984 ++++++++++++++++++++++
 3 files changed, 6350 insertions(+)

diff --git a/providers/cxi/cxi_telem.c b/providers/cxi/cxi_telem.c
new file mode 100644
index 000000000000..62d73e132377
--- /dev/null
+++ b/providers/cxi/cxi_telem.c
@@ -0,0 +1,3948 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <errno.h>
+#include <string.h>
+#include <ccan/array_size.h>
+
+#include <infiniband/cxidv_telem.h>
+
+static const char *const telem_names[CXIDV_TELEM_COUNT] = {
+	"UNDEFINED",
+	"atu_at_stall_ccp",
+	"atu_at_stall_no_ptid",
+	"atu_at_stall_np_cdts",
+	"atu_at_stall_tarb_arb",
+	"atu_ats_dynamic_state_change_cntr",
+	"atu_ats_inval_cntr",
+	"atu_ats_prs_odp_latency_0",
+	"atu_ats_prs_odp_latency_1",
+	"atu_ats_prs_odp_latency_2",
+	"atu_ats_prs_odp_latency_3",
+	"atu_ats_trans_err",
+	"atu_ats_trans_latency_0",
+	"atu_ats_trans_latency_1",
+	"atu_ats_trans_latency_2",
+	"atu_ats_trans_latency_3",
+	"atu_atucq_inval_cntr",
+	"atu_cache_evictions",
+	"atu_cache_hit_base_page_size_0",
+	"atu_cache_hit_base_page_size_1",
+	"atu_cache_hit_base_page_size_2",
+	"atu_cache_hit_base_page_size_3",
+	"atu_cache_hit_derivative1_page_size_0",
+	"atu_cache_hit_derivative1_page_size_1",
+	"atu_cache_hit_derivative1_page_size_2",
+	"atu_cache_hit_derivative1_page_size_3",
+	"atu_cache_hit_derivative2_page_size_0",
+	"atu_cache_hit_derivative2_page_size_1",
+	"atu_cache_hit_derivative2_page_size_2",
+	"atu_cache_hit_derivative2_page_size_3",
+	"atu_cache_miss_0",
+	"atu_cache_miss_1",
+	"atu_cache_miss_2",
+	"atu_cache_miss_3",
+	"atu_cache_miss_ee",
+	"atu_cache_miss_ixe",
+	"atu_cache_miss_oxe",
+	"atu_client_req_ee",
+	"atu_client_req_ixe",
+	"atu_client_req_oxe",
+	"atu_client_rsp_not_ok_0",
+	"atu_client_rsp_not_ok_1",
+	"atu_client_rsp_not_ok_2",
+	"atu_client_rsp_not_ok_3",
+	"atu_filtered_requests",
+	"atu_implicit_ats_en_inval_cntr",
+	"atu_implicit_flr_inval_cntr",
+	"atu_inval_stall_arb",
+	"atu_inval_stall_cmpl_wait",
+	"atu_mem_cor_err_cntr",
+	"atu_mem_ucor_err_cntr",
+	"atu_nic_pri_odp_latency_0",
+	"atu_nic_pri_odp_latency_1",
+	"atu_nic_pri_odp_latency_2",
+	"atu_nic_pri_odp_latency_3",
+	"atu_nta_trans_latency_0",
+	"atu_nta_trans_latency_1",
+	"atu_nta_trans_latency_2",
+	"atu_nta_trans_latency_3",
+	"atu_odp_requests_0",
+	"atu_odp_requests_1",
+	"atu_odp_requests_2",
+	"atu_odp_requests_3",
+	"atu_pcie_err_poisoned",
+	"atu_pcie_unsuccess_cmpl",
+	"cq_cfg_event_cnts_ovf_cnt",
+	"cq_cq_cmd_counts_0",
+	"cq_cq_cmd_counts_1",
+	"cq_cq_cmd_counts_2",
+	"cq_cq_cmd_counts_3",
+	"cq_cq_cmd_counts_4",
+	"cq_cq_cmd_counts_5",
+	"cq_cq_cmd_counts_6",
+	"cq_cq_cmd_counts_7",
+	"cq_cq_cmd_counts_8",
+	"cq_cq_cmd_counts_9",
+	"cq_cq_cmd_counts_10",
+	"cq_cq_cmd_counts_11",
+	"cq_cq_cmd_counts_12",
+	"cq_cq_cmd_counts_13",
+	"cq_cq_cmd_counts_14",
+	"cq_cq_cmd_counts_15",
+	"cq_cq_oxe_num_flits",
+	"cq_cq_oxe_num_idles",
+	"cq_cq_oxe_num_stalls",
+	"cq_cq_tou_num_flits",
+	"cq_cq_tou_num_idles",
+	"cq_cq_tou_num_stalls",
+	"cq_cycles_blocked_0",
+	"cq_cycles_blocked_1",
+	"cq_cycles_blocked_2",
+	"cq_cycles_blocked_3",
+	"cq_dma_cmd_counts_0",
+	"cq_dma_cmd_counts_1",
+	"cq_dma_cmd_counts_2",
+	"cq_dma_cmd_counts_3",
+	"cq_dma_cmd_counts_4",
+	"cq_dma_cmd_counts_5",
+	"cq_dma_cmd_counts_6",
+	"cq_dma_cmd_counts_7",
+	"cq_dma_cmd_counts_8",
+	"cq_dma_cmd_counts_9",
+	"cq_dma_cmd_counts_10",
+	"cq_dma_cmd_counts_11",
+	"cq_dma_cmd_counts_12",
+	"cq_dma_cmd_counts_13",
+	"cq_dma_cmd_counts_14",
+	"cq_dma_cmd_counts_15",
+	"cq_fail_tgt_cntr",
+	"cq_fail_tx_cntr",
+	"cq_mem_cor_err_cntr",
+	"cq_mem_ucor_err_cntr",
+	"cq_num_cq_cmds_0",
+	"cq_num_cq_cmds_1",
+	"cq_num_cq_cmds_2",
+	"cq_num_cq_cmds_3",
+	"cq_num_dma_cmds_0",
+	"cq_num_dma_cmds_1",
+	"cq_num_dma_cmds_2",
+	"cq_num_dma_cmds_3",
+	"cq_num_idc_cmds_0",
+	"cq_num_idc_cmds_1",
+	"cq_num_idc_cmds_2",
+	"cq_num_idc_cmds_3",
+	"cq_num_ll_cmds_0",
+	"cq_num_ll_cmds_1",
+	"cq_num_ll_cmds_2",
+	"cq_num_ll_cmds_3",
+	"cq_num_ll_ops_received_0",
+	"cq_num_ll_ops_received_1",
+	"cq_num_ll_ops_received_2",
+	"cq_num_ll_ops_received_3",
+	"cq_num_ll_ops_rejected_0",
+	"cq_num_ll_ops_rejected_1",
+	"cq_num_ll_ops_rejected_2",
+	"cq_num_ll_ops_rejected_3",
+	"cq_num_ll_ops_split_0",
+	"cq_num_ll_ops_split_1",
+	"cq_num_ll_ops_split_2",
+	"cq_num_ll_ops_split_3",
+	"cq_num_ll_ops_successful_0",
+	"cq_num_ll_ops_successful_1",
+	"cq_num_ll_ops_successful_2",
+	"cq_num_ll_ops_successful_3",
+	"cq_num_tgq_cmd_reads_0",
+	"cq_num_tgq_cmd_reads_1",
+	"cq_num_tgq_cmd_reads_2",
+	"cq_num_tgq_cmd_reads_3",
+	"cq_num_tgt_cmd_arg_errors",
+	"cq_num_tgt_cmd_perm_errors",
+	"cq_num_tgt_cmds_0",
+	"cq_num_tgt_cmds_1",
+	"cq_num_tgt_cmds_2",
+	"cq_num_tgt_cmds_3",
+	"cq_num_tou_cmd_reads_0",
+	"cq_num_tou_cmd_reads_1",
+	"cq_num_tou_cmd_reads_2",
+	"cq_num_tou_cmd_reads_3",
+	"cq_num_tx_cmd_align_errors",
+	"cq_num_tx_cmd_arg_errors",
+	"cq_num_tx_cmd_op_errors",
+	"cq_num_tx_cmd_perm_errors",
+	"cq_num_txq_cmd_reads_0",
+	"cq_num_txq_cmd_reads_1",
+	"cq_num_txq_cmd_reads_2",
+	"cq_num_txq_cmd_reads_3",
+	"cq_rarb_err_cntr",
+	"cq_rarb_ll_err_cntr",
+	"cq_sts_credits_in_use_ee_event_credits",
+	"cq_sts_credits_in_use_fq_sh_credits",
+	"cq_sts_credits_in_use_fq_tot_credits",
+	"cq_sts_credits_in_use_lpe_cmd_credits",
+	"cq_sts_credits_in_use_lpe_rcv_fifo_credits",
+	"cq_sts_credits_in_use_prefetch_tou_credits",
+	"cq_sts_credits_in_use_tarb_np_credits",
+	"cq_sts_credits_in_use_tarb_p_credits",
+	"cq_sts_credits_in_use_tgq_cmd_fail_event_credits",
+	"cq_sts_credits_in_use_tou_cmd_fail_event_credits",
+	"cq_sts_credits_in_use_tou_event_credits",
+	"cq_sts_credits_in_use_tou_fq_credits",
+	"cq_sts_credits_in_use_tou_wb_credits",
+	"cq_sts_credits_in_use_txq_cmd_fail_event_credits",
+	"cq_sts_dma_payload_data_0",
+	"cq_sts_dma_payload_data_1",
+	"cq_sts_dma_payload_data_2",
+	"cq_sts_dma_payload_data_3",
+	"cq_sts_fq_load_0",
+	"cq_sts_fq_load_1",
+	"cq_sts_fq_load_2",
+	"cq_sts_fq_load_3",
+	"cq_sts_fq_load_4",
+	"cq_sts_fq_load_5",
+	"cq_sts_fq_load_6",
+	"cq_sts_fq_load_7",
+	"cq_sts_fq_load_8",
+	"cq_sts_fq_load_9",
+	"cq_sts_fq_load_10",
+	"cq_sts_fq_load_11",
+	"cq_sts_fq_load_12",
+	"cq_sts_fq_load_13",
+	"cq_sts_fq_load_14",
+	"cq_sts_fq_load_15",
+	"cq_sts_fq_load_16",
+	"cq_sts_fq_load_17",
+	"cq_sts_fq_load_18",
+	"cq_sts_fq_load_19",
+	"cq_sts_fq_load_20",
+	"cq_sts_fq_load_21",
+	"cq_sts_fq_load_22",
+	"cq_sts_fq_load_23",
+	"cq_sts_fq_load_24",
+	"cq_sts_fq_load_25",
+	"cq_sts_fq_load_26",
+	"cq_sts_fq_load_27",
+	"cq_sts_fq_load_28",
+	"cq_sts_fq_load_29",
+	"cq_sts_fq_load_30",
+	"cq_sts_fq_load_31",
+	"cq_sts_fq_load_32",
+	"cq_sts_fq_load_33",
+	"cq_sts_fq_load_34",
+	"cq_sts_fq_load_35",
+	"cq_sts_fq_load_36",
+	"cq_sts_fq_load_37",
+	"cq_sts_fq_load_38",
+	"cq_sts_fq_load_39",
+	"cq_sts_fq_load_40",
+	"cq_sts_fq_load_41",
+	"cq_sts_fq_load_42",
+	"cq_sts_fq_load_43",
+	"cq_sts_fq_load_44",
+	"cq_sts_fq_load_45",
+	"cq_sts_fq_load_46",
+	"cq_sts_fq_load_47",
+	"cq_sts_idc_payload_data_0",
+	"cq_sts_idc_payload_data_1",
+	"cq_sts_idc_payload_data_2",
+	"cq_sts_idc_payload_data_3",
+	"cq_sts_ll_dma_payload_data_0",
+	"cq_sts_ll_dma_payload_data_1",
+	"cq_sts_ll_dma_payload_data_2",
+	"cq_sts_ll_dma_payload_data_3",
+	"cq_sts_ll_idc_payload_data_0",
+	"cq_sts_ll_idc_payload_data_1",
+	"cq_sts_ll_idc_payload_data_2",
+	"cq_sts_ll_idc_payload_data_3",
+	"cq_sts_tle_in_use_0",
+	"cq_sts_tle_in_use_1",
+	"cq_sts_tle_in_use_2",
+	"cq_sts_tle_in_use_3",
+	"cq_sts_tou_payload_data_0",
+	"cq_sts_tou_payload_data_1",
+	"cq_sts_tou_payload_data_2",
+	"cq_sts_tou_payload_data_3",
+	"cq_success_tgt_cntr",
+	"cq_success_tx_cntr",
+	"cq_tgt_waiting_on_read_0",
+	"cq_tgt_waiting_on_read_1",
+	"cq_tgt_waiting_on_read_2",
+	"cq_tgt_waiting_on_read_3",
+	"cq_tx_waiting_on_read_0",
+	"cq_tx_waiting_on_read_1",
+	"cq_tx_waiting_on_read_2",
+	"cq_tx_waiting_on_read_3",
+	"cq_wr_ptr_updt_err_cntr",
+	"ee_addr_trans_prefetch_cntr_0",
+	"ee_addr_trans_prefetch_cntr_1",
+	"ee_addr_trans_prefetch_cntr_2",
+	"ee_addr_trans_prefetch_cntr_3",
+	"ee_addr_trans_req_cntr",
+	"ee_cbs_written_cntr_0",
+	"ee_cbs_written_cntr_1",
+	"ee_cbs_written_cntr_2",
+	"ee_cbs_written_cntr_3",
+	"ee_ce_arb_out_event_cntr",
+	"ee_ce_arb_out_stall_cntr",
+	"ee_cq_event_req_cntr",
+	"ee_cq_fe_cntr",
+	"ee_cq_fe_stall_cntr",
+	"ee_deferred_eq_switch_cntr_0",
+	"ee_deferred_eq_switch_cntr_1",
+	"ee_deferred_eq_switch_cntr_2",
+	"ee_deferred_eq_switch_cntr_3",
+	"ee_eq_buffer_switch_cntr_0",
+	"ee_eq_buffer_switch_cntr_1",
+	"ee_eq_buffer_switch_cntr_2",
+	"ee_eq_buffer_switch_cntr_3",
+	"ee_eq_dsabld_event_err_cntr",
+	"ee_eq_dsabld_lpeq_err_cntr",
+	"ee_eq_dsabld_sws_err_cntr",
+	"ee_eq_rsrvn_uflw_err_cntr",
+	"ee_eq_state_ucor_err_cntr",
+	"ee_eq_status_update_cntr_0",
+	"ee_eq_status_update_cntr_1",
+	"ee_eq_status_update_cntr_2",
+	"ee_eq_status_update_cntr_3",
+	"ee_eq_sw_state_wr_cntr_0",
+	"ee_eq_sw_state_wr_cntr_1",
+	"ee_eq_sw_state_wr_cntr_2",
+	"ee_eq_sw_state_wr_cntr_3",
+	"ee_eqs_arb_out_req_cntr",
+	"ee_eqs_csr_req_cntr",
+	"ee_eqs_csr_stall_cntr",
+	"ee_eqs_event_req_cntr",
+	"ee_eqs_event_stall_cntr",
+	"ee_eqs_expired_cb_req_cntr",
+	"ee_eqs_expired_cb_stall_cntr",
+	"ee_eqs_free_cb_stall_cntr",
+	"ee_eqs_hws_init_req_cntr",
+	"ee_eqs_hws_init_stall_cntr",
+	"ee_eqs_lpe_query_req_cntr",
+	"ee_eqs_sts_updt_req_cntr",
+	"ee_eqs_sts_updt_stall_cntr",
+	"ee_eqs_sws_wr_req_cntr",
+	"ee_eqs_sws_wr_stall_cntr",
+	"ee_event_ack_cntr",
+	"ee_event_atomic_cntr",
+	"ee_event_atomic_overflow_cntr",
+	"ee_event_command_failure_cntr",
+	"ee_event_eq_switch_cntr",
+	"ee_event_error_cntr",
+	"ee_event_ethernet_cntr",
+	"ee_event_ethernet_fgfc_cntr",
+	"ee_event_fetch_atomic_cntr",
+	"ee_event_fetch_atomic_overflow_cntr",
+	"ee_event_get_cntr",
+	"ee_event_get_overflow_cntr",
+	"ee_event_link_cntr",
+	"ee_event_match_cntr",
+	"ee_event_null_event_cntr",
+	"ee_event_pct_cntr",
+	"ee_event_put_cntr",
+	"ee_event_put_overflow_cntr",
+	"ee_event_rendezvous_cntr",
+	"ee_event_reply_cntr",
+	"ee_event_search_cntr",
+	"ee_event_send_cntr",
+	"ee_event_state_change_cntr",
+	"ee_event_timestamp_cntr",
+	"ee_event_triggered_op_cntr",
+	"ee_event_unlink_cntr",
+	"ee_events_dropped_fc_sc_cntr_0",
+	"ee_events_dropped_fc_sc_cntr_1",
+	"ee_events_dropped_fc_sc_cntr_2",
+	"ee_events_dropped_fc_sc_cntr_3",
+	"ee_events_dropped_ordinary_cntr_0",
+	"ee_events_dropped_ordinary_cntr_1",
+	"ee_events_dropped_ordinary_cntr_2",
+	"ee_events_dropped_ordinary_cntr_3",
+	"ee_events_dropped_rsrvn_cntr_0",
+	"ee_events_dropped_rsrvn_cntr_1",
+	"ee_events_dropped_rsrvn_cntr_2",
+	"ee_events_dropped_rsrvn_cntr_3",
+	"ee_events_enqueued_cntr_0",
+	"ee_events_enqueued_cntr_1",
+	"ee_events_enqueued_cntr_2",
+	"ee_events_enqueued_cntr_3",
+	"ee_expired_cbs_written_cntr_0",
+	"ee_expired_cbs_written_cntr_1",
+	"ee_expired_cbs_written_cntr_2",
+	"ee_expired_cbs_written_cntr_3",
+	"ee_fe_arb_out_event_cntr",
+	"ee_fe_arb_out_stall_cntr",
+	"ee_hni_event_req_cntr",
+	"ee_hni_fe_cntr",
+	"ee_hni_fe_stall_cntr",
+	"ee_ixe_ce_cntr",
+	"ee_ixe_ce_stall_cntr",
+	"ee_ixe_dd_cntr",
+	"ee_ixe_event_req_cntr",
+	"ee_ixe_fe_cntr",
+	"ee_ixe_fe_stall_cntr",
+	"ee_lpe_ce_cntr",
+	"ee_lpe_ce_stall_cntr",
+	"ee_lpe_dd_cntr",
+	"ee_lpe_event_req_cntr",
+	"ee_lpe_fe_cntr",
+	"ee_lpe_fe_stall_cntr",
+	"ee_lpe_query_eq_none_cntr",
+	"ee_mem_cor_err_cntr",
+	"ee_mem_ucor_err_cntr",
+	"ee_mst_ce_cntr",
+	"ee_mst_ce_stall_cntr",
+	"ee_mst_dd_cntr",
+	"ee_mst_event_req_cntr",
+	"ee_mst_fe_cntr",
+	"ee_mst_fe_stall_cntr",
+	"ee_partial_cbs_written_cntr_0",
+	"ee_partial_cbs_written_cntr_1",
+	"ee_partial_cbs_written_cntr_2",
+	"ee_partial_cbs_written_cntr_3",
+	"ee_pct_ce_cntr",
+	"ee_pct_ce_stall_cntr",
+	"ee_pct_dd_cntr",
+	"ee_pct_event_req_cntr",
+	"ee_pct_fe_cntr",
+	"ee_pct_fe_stall_cntr",
+	"ee_rarb_hw_err_cntr",
+	"ee_rarb_sw_err_cntr",
+	"ee_sts_ecbs_in_use_ecbs_in_use",
+	"ee_sts_ecbs_in_use_max_ecbs_in_use",
+	"ee_tarb_err_cntr",
+	"ee_tarb_irq_req_cntr",
+	"ee_tarb_stall_cntr",
+	"ee_tarb_wr_req_cntr",
+	"ee_ts_fe_cntr",
+	"ee_ts_fe_stall_cntr",
+	"ee_unxpctd_trnsltn_rsp_err_cntr",
+	"hni_cfg_event_cnts_ovf_cnt",
+	"hni_cor_ecc_err_cntr",
+	"hni_discard_cntr_0",
+	"hni_discard_cntr_1",
+	"hni_discard_cntr_2",
+	"hni_discard_cntr_3",
+	"hni_discard_cntr_4",
+	"hni_discard_cntr_5",
+	"hni_discard_cntr_6",
+	"hni_discard_cntr_7",
+	"hni_fgfc_discard",
+	"hni_fgfc_event_xoff",
+	"hni_fgfc_event_xon",
+	"hni_fgfc_ipv4",
+	"hni_fgfc_ipv6",
+	"hni_fgfc_l2",
+	"hni_fgfc_match",
+	"hni_fgfc_port",
+	"hni_hrp_ack",
+	"hni_hrp_resp",
+	"hni_llr_rx_ack_ctl_os",
+	"hni_llr_rx_ack_nack_error",
+	"hni_llr_rx_ack_nack_seq_err",
+	"hni_llr_rx_bad_ctl_fr",
+	"hni_llr_rx_bad_lossless",
+	"hni_llr_rx_bad_lossy",
+	"hni_llr_rx_duplicate_seq",
+	"hni_llr_rx_expected_seq_bad",
+	"hni_llr_rx_expected_seq_good",
+	"hni_llr_rx_expected_seq_poisoned",
+	"hni_llr_rx_init_ctl_os",
+	"hni_llr_rx_init_echo_ctl_os",
+	"hni_llr_rx_loop_time_req_ctl_fr",
+	"hni_llr_rx_loop_time_rsp_ctl_fr",
+	"hni_llr_rx_nack_ctl_os",
+	"hni_llr_rx_ok_lossless",
+	"hni_llr_rx_ok_lossy",
+	"hni_llr_rx_poisoned_lossless",
+	"hni_llr_rx_poisoned_lossy",
+	"hni_llr_rx_replay_event",
+	"hni_llr_rx_unexpected_seq",
+	"hni_llr_tx_ack_ctl_os",
+	"hni_llr_tx_bad_lossless",
+	"hni_llr_tx_bad_lossless_rpt",
+	"hni_llr_tx_bad_lossy",
+	"hni_llr_tx_discard",
+	"hni_llr_tx_init_ctl_os",
+	"hni_llr_tx_init_echo_ctl_os",
+	"hni_llr_tx_llr_blocked",
+	"hni_llr_tx_llr_unblocked",
+	"hni_llr_tx_loop_time_req_ctl_fr",
+	"hni_llr_tx_loop_time_rsp_ctl_fr",
+	"hni_llr_tx_nack_ctl_os",
+	"hni_llr_tx_ok_bypass",
+	"hni_llr_tx_ok_lossless",
+	"hni_llr_tx_ok_lossless_rpt",
+	"hni_llr_tx_ok_lossy",
+	"hni_llr_tx_poisoned_lossless",
+	"hni_llr_tx_poisoned_lossless_rpt",
+	"hni_llr_tx_poisoned_lossy",
+	"hni_llr_tx_replay_event",
+	"hni_mac_rx_fragment",
+	"hni_mac_rx_illegal_size",
+	"hni_mac_rx_preamble_error",
+	"hni_mac_tx_ifg_adjustment_sync",
+	"hni_multicast_pkts_recv_by_tc_0",
+	"hni_multicast_pkts_recv_by_tc_1",
+	"hni_multicast_pkts_recv_by_tc_2",
+	"hni_multicast_pkts_recv_by_tc_3",
+	"hni_multicast_pkts_recv_by_tc_4",
+	"hni_multicast_pkts_recv_by_tc_5",
+	"hni_multicast_pkts_recv_by_tc_6",
+	"hni_multicast_pkts_recv_by_tc_7",
+	"hni_multicast_pkts_sent_by_tc_0",
+	"hni_multicast_pkts_sent_by_tc_1",
+	"hni_multicast_pkts_sent_by_tc_2",
+	"hni_multicast_pkts_sent_by_tc_3",
+	"hni_multicast_pkts_sent_by_tc_4",
+	"hni_multicast_pkts_sent_by_tc_5",
+	"hni_multicast_pkts_sent_by_tc_6",
+	"hni_multicast_pkts_sent_by_tc_7",
+	"hni_pause_recv_0",
+	"hni_pause_recv_1",
+	"hni_pause_recv_2",
+	"hni_pause_recv_3",
+	"hni_pause_recv_4",
+	"hni_pause_recv_5",
+	"hni_pause_recv_6",
+	"hni_pause_recv_7",
+	"hni_pause_refresh",
+	"hni_pause_sent",
+	"hni_pause_xoff_sent_0",
+	"hni_pause_xoff_sent_1",
+	"hni_pause_xoff_sent_2",
+	"hni_pause_xoff_sent_3",
+	"hni_pause_xoff_sent_4",
+	"hni_pause_xoff_sent_5",
+	"hni_pause_xoff_sent_6",
+	"hni_pause_xoff_sent_7",
+	"hni_pcs_corrected_cw",
+	"hni_pcs_corrected_cw_bin_0",
+	"hni_pcs_corrected_cw_bin_1",
+	"hni_pcs_corrected_cw_bin_2",
+	"hni_pcs_corrected_cw_bin_3",
+	"hni_pcs_corrected_cw_bin_4",
+	"hni_pcs_corrected_cw_bin_5",
+	"hni_pcs_corrected_cw_bin_6",
+	"hni_pcs_corrected_cw_bin_7",
+	"hni_pcs_corrected_cw_bin_8",
+	"hni_pcs_corrected_cw_bin_9",
+	"hni_pcs_corrected_cw_bin_10",
+	"hni_pcs_corrected_cw_bin_11",
+	"hni_pcs_corrected_cw_bin_12",
+	"hni_pcs_corrected_cw_bin_13",
+	"hni_pcs_corrected_cw_bin_14",
+	"hni_pcs_fecl_errors_0",
+	"hni_pcs_fecl_errors_1",
+	"hni_pcs_fecl_errors_2",
+	"hni_pcs_fecl_errors_3",
+	"hni_pcs_fecl_errors_4",
+	"hni_pcs_fecl_errors_5",
+	"hni_pcs_fecl_errors_6",
+	"hni_pcs_fecl_errors_7",
+	"hni_pcs_fecl_errors_8",
+	"hni_pcs_fecl_errors_9",
+	"hni_pcs_fecl_errors_10",
+	"hni_pcs_fecl_errors_11",
+	"hni_pcs_fecl_errors_12",
+	"hni_pcs_fecl_errors_13",
+	"hni_pcs_fecl_errors_14",
+	"hni_pcs_fecl_errors_15",
+	"hni_pcs_good_cw",
+	"hni_pcs_pml_mbe_error_cnt",
+	"hni_pcs_pml_sbe_error_cnt",
+	"hni_pcs_uncorrected_cw",
+	"hni_pfc_fifo_oflw_cntr_0",
+	"hni_pfc_fifo_oflw_cntr_1",
+	"hni_pfc_fifo_oflw_cntr_2",
+	"hni_pfc_fifo_oflw_cntr_3",
+	"hni_pfc_fifo_oflw_cntr_4",
+	"hni_pfc_fifo_oflw_cntr_5",
+	"hni_pfc_fifo_oflw_cntr_6",
+	"hni_pfc_fifo_oflw_cntr_7",
+	"hni_pkts_recv_by_tc_0",
+	"hni_pkts_recv_by_tc_1",
+	"hni_pkts_recv_by_tc_2",
+	"hni_pkts_recv_by_tc_3",
+	"hni_pkts_recv_by_tc_4",
+	"hni_pkts_recv_by_tc_5",
+	"hni_pkts_recv_by_tc_6",
+	"hni_pkts_recv_by_tc_7",
+	"hni_pkts_sent_by_tc_0",
+	"hni_pkts_sent_by_tc_1",
+	"hni_pkts_sent_by_tc_2",
+	"hni_pkts_sent_by_tc_3",
+	"hni_pkts_sent_by_tc_4",
+	"hni_pkts_sent_by_tc_5",
+	"hni_pkts_sent_by_tc_6",
+	"hni_pkts_sent_by_tc_7",
+	"hni_rx_bad_ieee",
+	"hni_rx_bad_opt",
+	"hni_rx_fragment",
+	"hni_rx_jabber",
+	"hni_rx_ok_27",
+	"hni_rx_ok_35",
+	"hni_rx_ok_36_to_63",
+	"hni_rx_ok_64",
+	"hni_rx_ok_65_to_127",
+	"hni_rx_ok_128_to_255",
+	"hni_rx_ok_256_to_511",
+	"hni_rx_ok_512_to_1023",
+	"hni_rx_ok_1024_to_2047",
+	"hni_rx_ok_2048_to_4095",
+	"hni_rx_ok_4096_to_8191",
+	"hni_rx_ok_8192_to_max",
+	"hni_rx_ok_bad_op_code",
+	"hni_rx_ok_broadcast",
+	"hni_rx_ok_flow_control",
+	"hni_rx_ok_ieee",
+	"hni_rx_ok_len_type_error",
+	"hni_rx_ok_mac_control",
+	"hni_rx_ok_multicast",
+	"hni_rx_ok_opt",
+	"hni_rx_ok_tagged",
+	"hni_rx_ok_too_long",
+	"hni_rx_ok_undersize",
+	"hni_rx_paused_0",
+	"hni_rx_paused_1",
+	"hni_rx_paused_2",
+	"hni_rx_paused_3",
+	"hni_rx_paused_4",
+	"hni_rx_paused_5",
+	"hni_rx_paused_6",
+	"hni_rx_paused_7",
+	"hni_rx_paused_std",
+	"hni_rx_stall_ixe_fifo",
+	"hni_rx_stall_ixe_pktbuf_0",
+	"hni_rx_stall_ixe_pktbuf_1",
+	"hni_rx_stall_ixe_pktbuf_2",
+	"hni_rx_stall_ixe_pktbuf_3",
+	"hni_rx_stall_ixe_pktbuf_4",
+	"hni_rx_stall_ixe_pktbuf_5",
+	"hni_rx_stall_ixe_pktbuf_6",
+	"hni_rx_stall_ixe_pktbuf_7",
+	"hni_sts_rx_bad_octets",
+	"hni_sts_rx_octets_bcast",
+	"hni_sts_rx_octets_ieee",
+	"hni_sts_rx_octets_multi",
+	"hni_sts_rx_octets_opt",
+	"hni_sts_rx_ok_octets",
+	"hni_sts_tx_bad_octets",
+	"hni_sts_tx_octets_bcast",
+	"hni_sts_tx_octets_ieee",
+	"hni_sts_tx_octets_multi",
+	"hni_sts_tx_octets_opt",
+	"hni_sts_tx_ok_octets",
+	"hni_tx_ok_27",
+	"hni_tx_ok_35",
+	"hni_tx_ok_36_to_63",
+	"hni_tx_ok_64",
+	"hni_tx_ok_65_to_127",
+	"hni_tx_ok_128_to_255",
+	"hni_tx_ok_256_to_511",
+	"hni_tx_ok_512_to_1023",
+	"hni_tx_ok_1024_to_2047",
+	"hni_tx_ok_2048_to_4095",
+	"hni_tx_ok_4096_to_8191",
+	"hni_tx_ok_8192_to_max",
+	"hni_tx_ok_broadcast",
+	"hni_tx_ok_ieee",
+	"hni_tx_ok_multicast",
+	"hni_tx_ok_opt",
+	"hni_tx_ok_tagged",
+	"hni_tx_opt_padded",
+	"hni_tx_opt_size_err",
+	"hni_tx_paused_0",
+	"hni_tx_paused_1",
+	"hni_tx_paused_2",
+	"hni_tx_paused_3",
+	"hni_tx_paused_4",
+	"hni_tx_paused_5",
+	"hni_tx_paused_6",
+	"hni_tx_paused_7",
+	"hni_tx_poisoned_ieee",
+	"hni_tx_poisoned_opt",
+	"hni_tx_stall_llr",
+	"hni_tx_std_padded",
+	"hni_tx_std_size_err",
+	"hni_ucor_ecc_err_cntr",
+	"ixe_disp_amo_conflicts",
+	"ixe_disp_amo_events",
+	"ixe_disp_atu_flush_reqs",
+	"ixe_disp_atu_reqs",
+	"ixe_disp_atu_resps",
+	"ixe_disp_atu_resps_ok",
+	"ixe_disp_dmawr_reqs",
+	"ixe_disp_dmawr_resps",
+	"ixe_disp_dmawr_resps_ok",
+	"ixe_disp_eth_events",
+	"ixe_disp_lpe_amos",
+	"ixe_disp_lpe_amos_ok",
+	"ixe_disp_lpe_gets",
+	"ixe_disp_lpe_gets_ok",
+	"ixe_disp_lpe_puts",
+	"ixe_disp_lpe_puts_ok",
+	"ixe_disp_mst_gets",
+	"ixe_disp_mst_gets_ok",
+	"ixe_disp_mst_puts",
+	"ixe_disp_mst_puts_ok",
+	"ixe_disp_oxe_resps",
+	"ixe_disp_pct_getcomp",
+	"ixe_disp_put_events",
+	"ixe_disp_rpu_err_reqs",
+	"ixe_disp_rpu_resps",
+	"ixe_disp_stall_atu_cdt",
+	"ixe_disp_stall_atu_fifo",
+	"ixe_disp_stall_conflict",
+	"ixe_disp_stall_err_fifo",
+	"ixe_disp_stall_gcomp_fifo",
+	"ixe_disp_stall_grr_id",
+	"ixe_disp_stall_mdid_cdts",
+	"ixe_disp_stall_mst_match_fifo",
+	"ixe_disp_stall_put_resp",
+	"ixe_disp_stall_resp_fifo",
+	"ixe_disp_wr_conflicts",
+	"ixe_dmawr_amo_ex_inexact",
+	"ixe_dmawr_amo_ex_invalid",
+	"ixe_dmawr_amo_ex_overflow",
+	"ixe_dmawr_amo_ex_underflow",
+	"ixe_dmawr_amo_invalid_op",
+	"ixe_dmawr_amo_len_err",
+	"ixe_dmawr_amo_misaligned",
+	"ixe_dmawr_cpu_amo_reqs",
+	"ixe_dmawr_cpu_ftch_amo_reqs",
+	"ixe_dmawr_flush_reqs",
+	"ixe_dmawr_nic_amo_reqs",
+	"ixe_dmawr_p_pass_np_cnt",
+	"ixe_dmawr_pcie_err_poisoned",
+	"ixe_dmawr_pcie_unsuccess_cmpl",
+	"ixe_dmawr_req_no_write_reqs",
+	"ixe_dmawr_stall_ftch_amo_cnt",
+	"ixe_dmawr_stall_np_cdt",
+	"ixe_dmawr_stall_np_req_cnt",
+	"ixe_dmawr_stall_p_cdt",
+	"ixe_dmawr_write_reqs",
+	"ixe_get_len_errors",
+	"ixe_hdr_checksum_errors",
+	"ixe_hdr_ecc_errors",
+	"ixe_hrp_req_errors",
+	"ixe_ip_options_errors",
+	"ixe_ipv4_checksum_errors",
+	"ixe_mem_cor_err_cntr",
+	"ixe_mem_ucor_err_cntr",
+	"ixe_parser_par_errors",
+	"ixe_pbuf_rd_errors",
+	"ixe_pool_ecn_pkts_0",
+	"ixe_pool_ecn_pkts_1",
+	"ixe_pool_ecn_pkts_2",
+	"ixe_pool_ecn_pkts_3",
+	"ixe_pool_no_ecn_pkts_0",
+	"ixe_pool_no_ecn_pkts_1",
+	"ixe_pool_no_ecn_pkts_2",
+	"ixe_pool_no_ecn_pkts_3",
+	"ixe_port_dfa_mismatch",
+	"ixe_roce_icrc_error",
+	"ixe_rx_eth_seg",
+	"ixe_rx_ipv4_pkt",
+	"ixe_rx_ipv6_pkt",
+	"ixe_rx_pkt_drop_ixe_parser",
+	"ixe_rx_pkt_drop_pct",
+	"ixe_rx_pkt_drop_rmu_norsp",
+	"ixe_rx_pkt_drop_rmu_wrsp",
+	"ixe_rx_pkt_ipv4_options",
+	"ixe_rx_pkt_ipv6_options",
+	"ixe_rx_ptl_connmgmt_pkt",
+	"ixe_rx_ptl_continuation_pkt",
+	"ixe_rx_ptl_gen_pkt",
+	"ixe_rx_ptl_mr_msgs",
+	"ixe_rx_ptl_msgs",
+	"ixe_rx_ptl_multi_msgs",
+	"ixe_rx_ptl_response_pkt",
+	"ixe_rx_ptl_restricted_pkt",
+	"ixe_rx_ptl_smallmsg_pkt",
+	"ixe_rx_ptl_sml_amo_pkt",
+	"ixe_rx_ptl_sml_pkt",
+	"ixe_rx_ptl_unrestricted_pkt",
+	"ixe_rx_roce_pkt",
+	"ixe_rx_roce_seg",
+	"ixe_rx_roce_spseg",
+	"ixe_rx_tcp_pkt",
+	"ixe_rx_udp_pkt",
+	"ixe_rx_unrecognized_pkt",
+	"ixe_tc_req_ecn_pkts_0",
+	"ixe_tc_req_ecn_pkts_1",
+	"ixe_tc_req_ecn_pkts_2",
+	"ixe_tc_req_ecn_pkts_3",
+	"ixe_tc_req_ecn_pkts_4",
+	"ixe_tc_req_ecn_pkts_5",
+	"ixe_tc_req_ecn_pkts_6",
+	"ixe_tc_req_ecn_pkts_7",
+	"ixe_tc_req_no_ecn_pkts_0",
+	"ixe_tc_req_no_ecn_pkts_1",
+	"ixe_tc_req_no_ecn_pkts_2",
+	"ixe_tc_req_no_ecn_pkts_3",
+	"ixe_tc_req_no_ecn_pkts_4",
+	"ixe_tc_req_no_ecn_pkts_5",
+	"ixe_tc_req_no_ecn_pkts_6",
+	"ixe_tc_req_no_ecn_pkts_7",
+	"ixe_tc_rsp_ecn_pkts_0",
+	"ixe_tc_rsp_ecn_pkts_1",
+	"ixe_tc_rsp_ecn_pkts_2",
+	"ixe_tc_rsp_ecn_pkts_3",
+	"ixe_tc_rsp_ecn_pkts_4",
+	"ixe_tc_rsp_ecn_pkts_5",
+	"ixe_tc_rsp_ecn_pkts_6",
+	"ixe_tc_rsp_ecn_pkts_7",
+	"ixe_tc_rsp_no_ecn_pkts_0",
+	"ixe_tc_rsp_no_ecn_pkts_1",
+	"ixe_tc_rsp_no_ecn_pkts_2",
+	"ixe_tc_rsp_no_ecn_pkts_3",
+	"ixe_tc_rsp_no_ecn_pkts_4",
+	"ixe_tc_rsp_no_ecn_pkts_5",
+	"ixe_tc_rsp_no_ecn_pkts_6",
+	"ixe_tc_rsp_no_ecn_pkts_7",
+	"lpe_amo_cmds",
+	"lpe_append_cmds_0",
+	"lpe_append_cmds_1",
+	"lpe_append_cmds_2",
+	"lpe_append_cmds_3",
+	"lpe_append_success_0",
+	"lpe_append_success_1",
+	"lpe_append_success_2",
+	"lpe_append_success_3",
+	"lpe_cfg_event_cnts_ovf_cnt",
+	"lpe_cfg_pe_le_shared_num_shared_0",
+	"lpe_cfg_pe_le_shared_num_shared_1",
+	"lpe_cfg_pe_le_shared_num_shared_2",
+	"lpe_cfg_pe_le_shared_num_shared_3",
+	"lpe_cfg_pe_le_shared_num_shared_allocated_0",
+	"lpe_cfg_pe_le_shared_num_shared_allocated_1",
+	"lpe_cfg_pe_le_shared_num_shared_allocated_2",
+	"lpe_cfg_pe_le_shared_num_shared_allocated_3",
+	"lpe_cfg_pe_le_shared_num_total_0",
+	"lpe_cfg_pe_le_shared_num_total_1",
+	"lpe_cfg_pe_le_shared_num_total_2",
+	"lpe_cfg_pe_le_shared_num_total_3",
+	"lpe_cfg_pe_le_shared_num_total_allocated_0",
+	"lpe_cfg_pe_le_shared_num_total_allocated_1",
+	"lpe_cfg_pe_le_shared_num_total_allocated_2",
+	"lpe_cfg_pe_le_shared_num_total_allocated_3",
+	"lpe_cyc_blocked_ixe_get",
+	"lpe_cyc_blocked_ixe_put",
+	"lpe_cyc_blocked_lossless",
+	"lpe_cyc_no_rdy_cdts",
+	"lpe_cyc_rrq_blocked_0",
+	"lpe_cyc_rrq_blocked_1",
+	"lpe_cyc_rrq_blocked_2",
+	"lpe_cyc_rrq_blocked_3",
+	"lpe_err_entry_not_found_cant_alloc_unexpected",
+	"lpe_err_entry_not_found_eq_full",
+	"lpe_err_entry_not_found_ethernet",
+	"lpe_err_entry_not_found_no_match_in_overflow",
+	"lpe_err_entry_not_found_req_empty",
+	"lpe_err_entry_not_found_unlink_failed",
+	"lpe_err_eq_disabled",
+	"lpe_err_illegal_op",
+	"lpe_err_invalid_endpoint",
+	"lpe_err_no_space_append",
+	"lpe_err_no_space_net",
+	"lpe_err_op_violation",
+	"lpe_err_pt_disabled_cant_alloc_unexpected",
+	"lpe_err_pt_disabled_eq_full",
+	"lpe_err_pt_disabled_no_match_in_overflow",
+	"lpe_err_pt_disabled_req_empty",
+	"lpe_err_ptlte_sw_managed",
+	"lpe_err_restricted_unicast",
+	"lpe_err_search_no_match",
+	"lpe_err_setstate_no_match",
+	"lpe_err_src_error",
+	"lpe_event_atomic_overflow",
+	"lpe_event_fetch_atomic_overflow",
+	"lpe_event_get_overflow",
+	"lpe_event_link",
+	"lpe_event_put_overflow",
+	"lpe_event_rendezvous",
+	"lpe_event_search",
+	"lpe_event_statechange",
+	"lpe_event_unlink",
+	"lpe_fail_cntr",
+	"lpe_famo_cmds",
+	"lpe_get_cmds",
+	"lpe_mem_cor_err_cntr",
+	"lpe_mem_ucor_err_cntr",
+	"lpe_net_match_local_0",
+	"lpe_net_match_local_1",
+	"lpe_net_match_local_2",
+	"lpe_net_match_local_3",
+	"lpe_net_match_overflow_0",
+	"lpe_net_match_overflow_1",
+	"lpe_net_match_overflow_2",
+	"lpe_net_match_overflow_3",
+	"lpe_net_match_priority_0",
+	"lpe_net_match_priority_1",
+	"lpe_net_match_priority_2",
+	"lpe_net_match_priority_3",
+	"lpe_net_match_request_0",
+	"lpe_net_match_request_1",
+	"lpe_net_match_request_2",
+	"lpe_net_match_request_3",
+	"lpe_net_match_requests_0",
+	"lpe_net_match_requests_1",
+	"lpe_net_match_requests_2",
+	"lpe_net_match_requests_3",
+	"lpe_net_match_success_0",
+	"lpe_net_match_success_1",
+	"lpe_net_match_success_2",
+	"lpe_net_match_success_3",
+	"lpe_net_match_useonce_0",
+	"lpe_net_match_useonce_1",
+	"lpe_net_match_useonce_2",
+	"lpe_net_match_useonce_3",
+	"lpe_num_truncated_0",
+	"lpe_num_truncated_1",
+	"lpe_num_truncated_2",
+	"lpe_num_truncated_3",
+	"lpe_plec_allocs",
+	"lpe_plec_frees",
+	"lpe_plec_frees_csr",
+	"lpe_plec_hits",
+	"lpe_put_cmds",
+	"lpe_rendezvous_put_cmds",
+	"lpe_rndzv_puts_0",
+	"lpe_rndzv_puts_1",
+	"lpe_rndzv_puts_2",
+	"lpe_rndzv_puts_3",
+	"lpe_rndzv_puts_offloaded_0",
+	"lpe_rndzv_puts_offloaded_1",
+	"lpe_rndzv_puts_offloaded_2",
+	"lpe_rndzv_puts_offloaded_3",
+	"lpe_search_cmds",
+	"lpe_search_delete_cmds",
+	"lpe_search_delete_fail",
+	"lpe_search_delete_success",
+	"lpe_search_fail",
+	"lpe_search_nid_any_0",
+	"lpe_search_nid_any_1",
+	"lpe_search_nid_any_2",
+	"lpe_search_nid_any_3",
+	"lpe_search_pid_any_0",
+	"lpe_search_pid_any_1",
+	"lpe_search_pid_any_2",
+	"lpe_search_pid_any_3",
+	"lpe_search_rank_any_0",
+	"lpe_search_rank_any_1",
+	"lpe_search_rank_any_2",
+	"lpe_search_rank_any_3",
+	"lpe_search_success",
+	"lpe_setstate_cmds_0",
+	"lpe_setstate_cmds_1",
+	"lpe_setstate_cmds_2",
+	"lpe_setstate_cmds_3",
+	"lpe_setstate_success_0",
+	"lpe_setstate_success_1",
+	"lpe_setstate_success_2",
+	"lpe_setstate_success_3",
+	"lpe_sts_app_match_attempts_0",
+	"lpe_sts_app_match_attempts_1",
+	"lpe_sts_app_match_attempts_2",
+	"lpe_sts_app_match_attempts_3",
+	"lpe_sts_app_max_attempts_max_0",
+	"lpe_sts_app_max_attempts_max_1",
+	"lpe_sts_app_max_attempts_max_2",
+	"lpe_sts_app_max_attempts_max_3",
+	"lpe_sts_app_max_attempts_num_pbuf_entries_0",
+	"lpe_sts_app_max_attempts_num_pbuf_entries_1",
+	"lpe_sts_app_max_attempts_num_pbuf_entries_2",
+	"lpe_sts_app_max_attempts_num_pbuf_entries_3",
+	"lpe_sts_load_stats_load_0",
+	"lpe_sts_load_stats_load_1",
+	"lpe_sts_load_stats_load_2",
+	"lpe_sts_load_stats_load_3",
+	"lpe_sts_load_stats_max_0",
+	"lpe_sts_load_stats_max_1",
+	"lpe_sts_load_stats_max_2",
+	"lpe_sts_load_stats_max_3",
+	"lpe_sts_load_stats_ptlte_load_0",
+	"lpe_sts_load_stats_ptlte_load_1",
+	"lpe_sts_load_stats_ptlte_load_2",
+	"lpe_sts_load_stats_ptlte_load_3",
+	"lpe_sts_load_stats_ptlte_max_0",
+	"lpe_sts_load_stats_ptlte_max_1",
+	"lpe_sts_load_stats_ptlte_max_2",
+	"lpe_sts_load_stats_ptlte_max_3",
+	"lpe_sts_net_match_attempts_0",
+	"lpe_sts_net_match_attempts_1",
+	"lpe_sts_net_match_attempts_2",
+	"lpe_sts_net_match_attempts_3",
+	"lpe_sts_net_max_attempts_max_0",
+	"lpe_sts_net_max_attempts_max_1",
+	"lpe_sts_net_max_attempts_max_2",
+	"lpe_sts_net_max_attempts_max_3",
+	"lpe_sts_net_max_attempts_num_pbuf_entries_0",
+	"lpe_sts_net_max_attempts_num_pbuf_entries_1",
+	"lpe_sts_net_max_attempts_num_pbuf_entries_2",
+	"lpe_sts_net_max_attempts_num_pbuf_entries_3",
+	"lpe_sts_pe_le_alloc_num_allocated_0",
+	"lpe_sts_pe_le_alloc_num_allocated_1",
+	"lpe_sts_pe_le_alloc_num_allocated_2",
+	"lpe_sts_pe_le_alloc_num_allocated_3",
+	"lpe_sts_pe_le_alloc_num_allocated_4",
+	"lpe_sts_pe_le_alloc_num_allocated_5",
+	"lpe_sts_pe_le_alloc_num_allocated_6",
+	"lpe_sts_pe_le_alloc_num_allocated_7",
+	"lpe_sts_pe_le_alloc_num_allocated_8",
+	"lpe_sts_pe_le_alloc_num_allocated_9",
+	"lpe_sts_pe_le_alloc_num_allocated_10",
+	"lpe_sts_pe_le_alloc_num_allocated_11",
+	"lpe_sts_pe_le_alloc_num_allocated_12",
+	"lpe_sts_pe_le_alloc_num_allocated_13",
+	"lpe_sts_pe_le_alloc_num_allocated_14",
+	"lpe_sts_pe_le_alloc_num_allocated_15",
+	"lpe_sts_pe_le_alloc_num_allocated_16",
+	"lpe_sts_pe_le_alloc_num_allocated_17",
+	"lpe_sts_pe_le_alloc_num_allocated_18",
+	"lpe_sts_pe_le_alloc_num_allocated_19",
+	"lpe_sts_pe_le_alloc_num_allocated_20",
+	"lpe_sts_pe_le_alloc_num_allocated_21",
+	"lpe_sts_pe_le_alloc_num_allocated_22",
+	"lpe_sts_pe_le_alloc_num_allocated_23",
+	"lpe_sts_pe_le_alloc_num_allocated_24",
+	"lpe_sts_pe_le_alloc_num_allocated_25",
+	"lpe_sts_pe_le_alloc_num_allocated_26",
+	"lpe_sts_pe_le_alloc_num_allocated_27",
+	"lpe_sts_pe_le_alloc_num_allocated_28",
+	"lpe_sts_pe_le_alloc_num_allocated_29",
+	"lpe_sts_pe_le_alloc_num_allocated_30",
+	"lpe_sts_pe_le_alloc_num_allocated_31",
+	"lpe_sts_pe_le_alloc_num_allocated_32",
+	"lpe_sts_pe_le_alloc_num_allocated_33",
+	"lpe_sts_pe_le_alloc_num_allocated_34",
+	"lpe_sts_pe_le_alloc_num_allocated_35",
+	"lpe_sts_pe_le_alloc_num_allocated_36",
+	"lpe_sts_pe_le_alloc_num_allocated_37",
+	"lpe_sts_pe_le_alloc_num_allocated_38",
+	"lpe_sts_pe_le_alloc_num_allocated_39",
+	"lpe_sts_pe_le_alloc_num_allocated_40",
+	"lpe_sts_pe_le_alloc_num_allocated_41",
+	"lpe_sts_pe_le_alloc_num_allocated_42",
+	"lpe_sts_pe_le_alloc_num_allocated_43",
+	"lpe_sts_pe_le_alloc_num_allocated_44",
+	"lpe_sts_pe_le_alloc_num_allocated_45",
+	"lpe_sts_pe_le_alloc_num_allocated_46",
+	"lpe_sts_pe_le_alloc_num_allocated_47",
+	"lpe_sts_pe_le_alloc_num_allocated_48",
+	"lpe_sts_pe_le_alloc_num_allocated_49",
+	"lpe_sts_pe_le_alloc_num_allocated_50",
+	"lpe_sts_pe_le_alloc_num_allocated_51",
+	"lpe_sts_pe_le_alloc_num_allocated_52",
+	"lpe_sts_pe_le_alloc_num_allocated_53",
+	"lpe_sts_pe_le_alloc_num_allocated_54",
+	"lpe_sts_pe_le_alloc_num_allocated_55",
+	"lpe_sts_pe_le_alloc_num_allocated_56",
+	"lpe_sts_pe_le_alloc_num_allocated_57",
+	"lpe_sts_pe_le_alloc_num_allocated_58",
+	"lpe_sts_pe_le_alloc_num_allocated_59",
+	"lpe_sts_pe_le_alloc_num_allocated_60",
+	"lpe_sts_pe_le_alloc_num_allocated_61",
+	"lpe_sts_pe_le_alloc_num_allocated_62",
+	"lpe_sts_pe_le_alloc_num_allocated_63",
+	"lpe_success_cntr",
+	"lpe_unexpected_get_amo_0",
+	"lpe_unexpected_get_amo_1",
+	"lpe_unexpected_get_amo_2",
+	"lpe_unexpected_get_amo_3",
+	"lpe_unlink_cmds",
+	"lpe_unlink_success",
+	"mb_cfg_event_cnts_ovf_cnt",
+	"mb_cmc_axi_rd_requests_0",
+	"mb_cmc_axi_rd_requests_1",
+	"mb_cmc_axi_rd_requests_2",
+	"mb_cmc_axi_rd_requests_3",
+	"mb_cmc_axi_wr_requests_0",
+	"mb_cmc_axi_wr_requests_1",
+	"mb_cmc_axi_wr_requests_2",
+	"mb_cmc_axi_wr_requests_3",
+	"mb_cq_lsa0_trigger_events_0",
+	"mb_cq_lsa0_trigger_events_1",
+	"mb_cq_lsa1_trigger_events_0",
+	"mb_cq_lsa1_trigger_events_1",
+	"mb_crmc_axi_rd_requests_0",
+	"mb_crmc_axi_rd_requests_1",
+	"mb_crmc_axi_rd_requests_2",
+	"mb_crmc_axi_wr_requests_0",
+	"mb_crmc_axi_wr_requests_1",
+	"mb_crmc_axi_wr_requests_2",
+	"mb_crmc_rd_error_0",
+	"mb_crmc_rd_error_1",
+	"mb_crmc_rd_error_2",
+	"mb_crmc_ring_mbe_0",
+	"mb_crmc_ring_mbe_1",
+	"mb_crmc_ring_mbe_2",
+	"mb_crmc_ring_rd_requests_0",
+	"mb_crmc_ring_rd_requests_1",
+	"mb_crmc_ring_rd_requests_2",
+	"mb_crmc_ring_sbe_0",
+	"mb_crmc_ring_sbe_1",
+	"mb_crmc_ring_sbe_2",
+	"mb_crmc_ring_wr_requests_0",
+	"mb_crmc_ring_wr_requests_1",
+	"mb_crmc_ring_wr_requests_2",
+	"mb_crmc_wr_error_0",
+	"mb_crmc_wr_error_1",
+	"mb_crmc_wr_error_2",
+	"mb_ee_lsa0_trigger_events_0",
+	"mb_ee_lsa0_trigger_events_1",
+	"mb_ee_lsa1_trigger_events_0",
+	"mb_ee_lsa1_trigger_events_1",
+	"mb_ixe_lsa0_trigger_events_0",
+	"mb_ixe_lsa0_trigger_events_1",
+	"mb_ixe_lsa1_trigger_events_0",
+	"mb_ixe_lsa1_trigger_events_1",
+	"mb_jai_axi_rd_requests",
+	"mb_jai_axi_wr_requests",
+	"mb_mb_lsa0_trigger_events_0",
+	"mb_mb_lsa0_trigger_events_1",
+	"mb_mb_lsa1_trigger_events_0",
+	"mb_mb_lsa1_trigger_events_1",
+	"mst_allocations",
+	"mst_err_cancelled",
+	"mst_mem_cor_err_cntr",
+	"mst_mem_ucor_err_cntr",
+	"mst_requests",
+	"mst_stalled_waiting_ee_crdts",
+	"mst_stalled_waiting_for_lpe",
+	"mst_stalled_waiting_get_crdts",
+	"mst_stalled_waiting_put_crdts",
+	"mst_sts_num_req",
+	"oxe_channel_idle",
+	"oxe_err_invalid_ac",
+	"oxe_err_no_translation",
+	"oxe_err_page_perm",
+	"oxe_err_page_req",
+	"oxe_err_pci_cmpl",
+	"oxe_err_pci_ep",
+	"oxe_err_ta_error",
+	"oxe_ignore_errs",
+	"oxe_ioi_dma",
+	"oxe_ioi_pkts_ordered",
+	"oxe_ioi_pkts_unordered",
+	"oxe_mcu_meas_0",
+	"oxe_mcu_meas_1",
+	"oxe_mcu_meas_2",
+	"oxe_mcu_meas_3",
+	"oxe_mcu_meas_4",
+	"oxe_mcu_meas_5",
+	"oxe_mcu_meas_6",
+	"oxe_mcu_meas_7",
+	"oxe_mcu_meas_8",
+	"oxe_mcu_meas_9",
+	"oxe_mcu_meas_10",
+	"oxe_mcu_meas_11",
+	"oxe_mcu_meas_12",
+	"oxe_mcu_meas_13",
+	"oxe_mcu_meas_14",
+	"oxe_mcu_meas_15",
+	"oxe_mcu_meas_16",
+	"oxe_mcu_meas_17",
+	"oxe_mcu_meas_18",
+	"oxe_mcu_meas_19",
+	"oxe_mcu_meas_20",
+	"oxe_mcu_meas_21",
+	"oxe_mcu_meas_22",
+	"oxe_mcu_meas_23",
+	"oxe_mcu_meas_24",
+	"oxe_mcu_meas_25",
+	"oxe_mcu_meas_26",
+	"oxe_mcu_meas_27",
+	"oxe_mcu_meas_28",
+	"oxe_mcu_meas_29",
+	"oxe_mcu_meas_30",
+	"oxe_mcu_meas_31",
+	"oxe_mcu_meas_32",
+	"oxe_mcu_meas_33",
+	"oxe_mcu_meas_34",
+	"oxe_mcu_meas_35",
+	"oxe_mcu_meas_36",
+	"oxe_mcu_meas_37",
+	"oxe_mcu_meas_38",
+	"oxe_mcu_meas_39",
+	"oxe_mcu_meas_40",
+	"oxe_mcu_meas_41",
+	"oxe_mcu_meas_42",
+	"oxe_mcu_meas_43",
+	"oxe_mcu_meas_44",
+	"oxe_mcu_meas_45",
+	"oxe_mcu_meas_46",
+	"oxe_mcu_meas_47",
+	"oxe_mcu_meas_48",
+	"oxe_mcu_meas_49",
+	"oxe_mcu_meas_50",
+	"oxe_mcu_meas_51",
+	"oxe_mcu_meas_52",
+	"oxe_mcu_meas_53",
+	"oxe_mcu_meas_54",
+	"oxe_mcu_meas_55",
+	"oxe_mcu_meas_56",
+	"oxe_mcu_meas_57",
+	"oxe_mcu_meas_58",
+	"oxe_mcu_meas_59",
+	"oxe_mcu_meas_60",
+	"oxe_mcu_meas_61",
+	"oxe_mcu_meas_62",
+	"oxe_mcu_meas_63",
+	"oxe_mcu_meas_64",
+	"oxe_mcu_meas_65",
+	"oxe_mcu_meas_66",
+	"oxe_mcu_meas_67",
+	"oxe_mcu_meas_68",
+	"oxe_mcu_meas_69",
+	"oxe_mcu_meas_70",
+	"oxe_mcu_meas_71",
+	"oxe_mcu_meas_72",
+	"oxe_mcu_meas_73",
+	"oxe_mcu_meas_74",
+	"oxe_mcu_meas_75",
+	"oxe_mcu_meas_76",
+	"oxe_mcu_meas_77",
+	"oxe_mcu_meas_78",
+	"oxe_mcu_meas_79",
+	"oxe_mcu_meas_80",
+	"oxe_mcu_meas_81",
+	"oxe_mcu_meas_82",
+	"oxe_mcu_meas_83",
+	"oxe_mcu_meas_84",
+	"oxe_mcu_meas_85",
+	"oxe_mcu_meas_86",
+	"oxe_mcu_meas_87",
+	"oxe_mcu_meas_88",
+	"oxe_mcu_meas_89",
+	"oxe_mcu_meas_90",
+	"oxe_mcu_meas_91",
+	"oxe_mcu_meas_92",
+	"oxe_mcu_meas_93",
+	"oxe_mcu_meas_94",
+	"oxe_mcu_meas_95",
+	"oxe_mem_cor_err_cntr",
+	"oxe_mem_ucor_err_cntr",
+	"oxe_num_hrp_cmds",
+	"oxe_prf_set0_occ_hist_bin0",
+	"oxe_prf_set0_occ_hist_bin1",
+	"oxe_prf_set0_occ_hist_bin2",
+	"oxe_prf_set0_occ_hist_bin3",
+	"oxe_prf_set0_pktbuf_na",
+	"oxe_prf_set0_smt_na",
+	"oxe_prf_set0_spt_na",
+	"oxe_prf_set0_srb_na",
+	"oxe_prf_set0_st_dma_mdr",
+	"oxe_prf_set0_st_dma_upd",
+	"oxe_prf_set0_st_header",
+	"oxe_prf_set0_st_pct_idx_wait",
+	"oxe_prf_set0_st_pktbuf_gnt",
+	"oxe_prf_set0_st_pktbuf_req",
+	"oxe_prf_set0_st_ready",
+	"oxe_prf_set0_ts_select",
+	"oxe_prf_set1_occ_hist_bin0",
+	"oxe_prf_set1_occ_hist_bin1",
+	"oxe_prf_set1_occ_hist_bin2",
+	"oxe_prf_set1_occ_hist_bin3",
+	"oxe_prf_set1_pktbuf_na",
+	"oxe_prf_set1_smt_na",
+	"oxe_prf_set1_spt_na",
+	"oxe_prf_set1_srb_na",
+	"oxe_prf_set1_st_dma_mdr",
+	"oxe_prf_set1_st_dma_upd",
+	"oxe_prf_set1_st_header",
+	"oxe_prf_set1_st_pct_idx_wait",
+	"oxe_prf_set1_st_pktbuf_gnt",
+	"oxe_prf_set1_st_pktbuf_req",
+	"oxe_prf_set1_st_ready",
+	"oxe_prf_set1_ts_select",
+	"oxe_ptl_tx_get_msgs_tsc_0",
+	"oxe_ptl_tx_get_msgs_tsc_1",
+	"oxe_ptl_tx_get_msgs_tsc_2",
+	"oxe_ptl_tx_get_msgs_tsc_3",
+	"oxe_ptl_tx_get_msgs_tsc_4",
+	"oxe_ptl_tx_get_msgs_tsc_5",
+	"oxe_ptl_tx_get_msgs_tsc_6",
+	"oxe_ptl_tx_get_msgs_tsc_7",
+	"oxe_ptl_tx_get_msgs_tsc_8",
+	"oxe_ptl_tx_get_msgs_tsc_9",
+	"oxe_ptl_tx_mr_msgs",
+	"oxe_ptl_tx_put_msgs_tsc_0",
+	"oxe_ptl_tx_put_msgs_tsc_1",
+	"oxe_ptl_tx_put_msgs_tsc_2",
+	"oxe_ptl_tx_put_msgs_tsc_3",
+	"oxe_ptl_tx_put_msgs_tsc_4",
+	"oxe_ptl_tx_put_msgs_tsc_5",
+	"oxe_ptl_tx_put_msgs_tsc_6",
+	"oxe_ptl_tx_put_msgs_tsc_7",
+	"oxe_ptl_tx_put_msgs_tsc_8",
+	"oxe_ptl_tx_put_msgs_tsc_9",
+	"oxe_ptl_tx_put_pkts_tsc_0",
+	"oxe_ptl_tx_put_pkts_tsc_1",
+	"oxe_ptl_tx_put_pkts_tsc_2",
+	"oxe_ptl_tx_put_pkts_tsc_3",
+	"oxe_ptl_tx_put_pkts_tsc_4",
+	"oxe_ptl_tx_put_pkts_tsc_5",
+	"oxe_ptl_tx_put_pkts_tsc_6",
+	"oxe_ptl_tx_put_pkts_tsc_7",
+	"oxe_ptl_tx_put_pkts_tsc_8",
+	"oxe_ptl_tx_put_pkts_tsc_9",
+	"oxe_smt_cdt_errs",
+	"oxe_spt_cdt_errs",
+	"oxe_stall_fgfc_blk_0",
+	"oxe_stall_fgfc_blk_1",
+	"oxe_stall_fgfc_blk_2",
+	"oxe_stall_fgfc_blk_3",
+	"oxe_stall_fgfc_cntrl_0",
+	"oxe_stall_fgfc_cntrl_1",
+	"oxe_stall_fgfc_cntrl_2",
+	"oxe_stall_fgfc_cntrl_3",
+	"oxe_stall_fgfc_end_0",
+	"oxe_stall_fgfc_end_1",
+	"oxe_stall_fgfc_end_2",
+	"oxe_stall_fgfc_end_3",
+	"oxe_stall_fgfc_start_0",
+	"oxe_stall_fgfc_start_1",
+	"oxe_stall_fgfc_start_2",
+	"oxe_stall_fgfc_start_3",
+	"oxe_stall_hdr_arb",
+	"oxe_stall_idc_cmd_no_deq",
+	"oxe_stall_idc_no_buff_bc_0",
+	"oxe_stall_idc_no_buff_bc_1",
+	"oxe_stall_idc_no_buff_bc_2",
+	"oxe_stall_idc_no_buff_bc_3",
+	"oxe_stall_idc_no_buff_bc_4",
+	"oxe_stall_idc_no_buff_bc_5",
+	"oxe_stall_idc_no_buff_bc_6",
+	"oxe_stall_idc_no_buff_bc_7",
+	"oxe_stall_idc_no_buff_bc_8",
+	"oxe_stall_idc_no_buff_bc_9",
+	"oxe_stall_ioi_last_ordered",
+	"oxe_stall_non_idc_cmd_no_deq",
+	"oxe_stall_pbuf_bc_0",
+	"oxe_stall_pbuf_bc_1",
+	"oxe_stall_pbuf_bc_2",
+	"oxe_stall_pbuf_bc_3",
+	"oxe_stall_pbuf_bc_4",
+	"oxe_stall_pbuf_bc_5",
+	"oxe_stall_pbuf_bc_6",
+	"oxe_stall_pbuf_bc_7",
+	"oxe_stall_pbuf_bc_8",
+	"oxe_stall_pbuf_bc_9",
+	"oxe_stall_pcie_scoreboard",
+	"oxe_stall_pct_bc_0",
+	"oxe_stall_pct_bc_1",
+	"oxe_stall_pct_bc_2",
+	"oxe_stall_pct_bc_3",
+	"oxe_stall_pct_bc_4",
+	"oxe_stall_pct_bc_5",
+	"oxe_stall_pct_bc_6",
+	"oxe_stall_pct_bc_7",
+	"oxe_stall_pct_bc_8",
+	"oxe_stall_pct_bc_9",
+	"oxe_stall_stfwd_eop",
+	"oxe_stall_ts_no_in_crd_tsc_0",
+	"oxe_stall_ts_no_in_crd_tsc_1",
+	"oxe_stall_ts_no_in_crd_tsc_2",
+	"oxe_stall_ts_no_in_crd_tsc_3",
+	"oxe_stall_ts_no_in_crd_tsc_4",
+	"oxe_stall_ts_no_in_crd_tsc_5",
+	"oxe_stall_ts_no_in_crd_tsc_6",
+	"oxe_stall_ts_no_in_crd_tsc_7",
+	"oxe_stall_ts_no_in_crd_tsc_8",
+	"oxe_stall_ts_no_in_crd_tsc_9",
+	"oxe_stall_ts_no_out_crd_tsc_0",
+	"oxe_stall_ts_no_out_crd_tsc_1",
+	"oxe_stall_ts_no_out_crd_tsc_2",
+	"oxe_stall_ts_no_out_crd_tsc_3",
+	"oxe_stall_ts_no_out_crd_tsc_4",
+	"oxe_stall_ts_no_out_crd_tsc_5",
+	"oxe_stall_ts_no_out_crd_tsc_6",
+	"oxe_stall_ts_no_out_crd_tsc_7",
+	"oxe_stall_ts_no_out_crd_tsc_8",
+	"oxe_stall_ts_no_out_crd_tsc_9",
+	"oxe_stall_with_no_atu_tag",
+	"oxe_stall_with_no_pci_tag",
+	"oxe_stall_wr_conflict_pkt_buff_bnk_0",
+	"oxe_stall_wr_conflict_pkt_buff_bnk_1",
+	"oxe_stall_wr_conflict_pkt_buff_bnk_2",
+	"oxe_stall_wr_conflict_pkt_buff_bnk_3",
+	"oxe_sts_bc_occ_bc_idc_shared_0",
+	"oxe_sts_bc_occ_bc_idc_shared_1",
+	"oxe_sts_bc_occ_bc_idc_shared_2",
+	"oxe_sts_bc_occ_bc_idc_shared_3",
+	"oxe_sts_bc_occ_bc_idc_shared_4",
+	"oxe_sts_bc_occ_bc_idc_shared_5",
+	"oxe_sts_bc_occ_bc_idc_shared_6",
+	"oxe_sts_bc_occ_bc_idc_shared_7",
+	"oxe_sts_bc_occ_bc_idc_shared_8",
+	"oxe_sts_bc_occ_bc_idc_shared_9",
+	"oxe_sts_bc_occ_bc_reserved_0",
+	"oxe_sts_bc_occ_bc_reserved_1",
+	"oxe_sts_bc_occ_bc_reserved_2",
+	"oxe_sts_bc_occ_bc_reserved_3",
+	"oxe_sts_bc_occ_bc_reserved_4",
+	"oxe_sts_bc_occ_bc_reserved_5",
+	"oxe_sts_bc_occ_bc_reserved_6",
+	"oxe_sts_bc_occ_bc_reserved_7",
+	"oxe_sts_bc_occ_bc_reserved_8",
+	"oxe_sts_bc_occ_bc_reserved_9",
+	"oxe_sts_bc_occ_bc_shared_0",
+	"oxe_sts_bc_occ_bc_shared_1",
+	"oxe_sts_bc_occ_bc_shared_2",
+	"oxe_sts_bc_occ_bc_shared_3",
+	"oxe_sts_bc_occ_bc_shared_4",
+	"oxe_sts_bc_occ_bc_shared_5",
+	"oxe_sts_bc_occ_bc_shared_6",
+	"oxe_sts_bc_occ_bc_shared_7",
+	"oxe_sts_bc_occ_bc_shared_8",
+	"oxe_sts_bc_occ_bc_shared_9",
+	"oxe_sts_mcu_occ_idc_cell_count_0",
+	"oxe_sts_mcu_occ_idc_cell_count_1",
+	"oxe_sts_mcu_occ_idc_cell_count_2",
+	"oxe_sts_mcu_occ_idc_cell_count_3",
+	"oxe_sts_mcu_occ_idc_cell_count_4",
+	"oxe_sts_mcu_occ_idc_cell_count_5",
+	"oxe_sts_mcu_occ_idc_cell_count_6",
+	"oxe_sts_mcu_occ_idc_cell_count_7",
+	"oxe_sts_mcu_occ_idc_cell_count_8",
+	"oxe_sts_mcu_occ_idc_cell_count_9",
+	"oxe_sts_mcu_occ_idc_cell_count_10",
+	"oxe_sts_mcu_occ_idc_cell_count_11",
+	"oxe_sts_mcu_occ_idc_cell_count_12",
+	"oxe_sts_mcu_occ_idc_cell_count_13",
+	"oxe_sts_mcu_occ_idc_cell_count_14",
+	"oxe_sts_mcu_occ_idc_cell_count_15",
+	"oxe_sts_mcu_occ_idc_cell_count_16",
+	"oxe_sts_mcu_occ_idc_cell_count_17",
+	"oxe_sts_mcu_occ_idc_cell_count_18",
+	"oxe_sts_mcu_occ_idc_cell_count_19",
+	"oxe_sts_mcu_occ_idc_cell_count_20",
+	"oxe_sts_mcu_occ_idc_cell_count_21",
+	"oxe_sts_mcu_occ_idc_cell_count_22",
+	"oxe_sts_mcu_occ_idc_cell_count_23",
+	"oxe_sts_mcu_occ_idc_cell_count_24",
+	"oxe_sts_mcu_occ_idc_cell_count_25",
+	"oxe_sts_mcu_occ_idc_cell_count_26",
+	"oxe_sts_mcu_occ_idc_cell_count_27",
+	"oxe_sts_mcu_occ_idc_cell_count_28",
+	"oxe_sts_mcu_occ_idc_cell_count_29",
+	"oxe_sts_mcu_occ_idc_cell_count_30",
+	"oxe_sts_mcu_occ_idc_cell_count_31",
+	"oxe_sts_mcu_occ_idc_cell_count_32",
+	"oxe_sts_mcu_occ_idc_cell_count_33",
+	"oxe_sts_mcu_occ_idc_cell_count_34",
+	"oxe_sts_mcu_occ_idc_cell_count_35",
+	"oxe_sts_mcu_occ_idc_cell_count_36",
+	"oxe_sts_mcu_occ_idc_cell_count_37",
+	"oxe_sts_mcu_occ_idc_cell_count_38",
+	"oxe_sts_mcu_occ_idc_cell_count_39",
+	"oxe_sts_mcu_occ_idc_cell_count_40",
+	"oxe_sts_mcu_occ_idc_cell_count_41",
+	"oxe_sts_mcu_occ_idc_cell_count_42",
+	"oxe_sts_mcu_occ_idc_cell_count_43",
+	"oxe_sts_mcu_occ_idc_cell_count_44",
+	"oxe_sts_mcu_occ_idc_cell_count_45",
+	"oxe_sts_mcu_occ_idc_cell_count_46",
+	"oxe_sts_mcu_occ_idc_cell_count_47",
+	"oxe_sts_mcu_occ_idc_cell_count_48",
+	"oxe_sts_mcu_occ_idc_cell_count_49",
+	"oxe_sts_mcu_occ_idc_cell_count_50",
+	"oxe_sts_mcu_occ_idc_cell_count_51",
+	"oxe_sts_mcu_occ_idc_cell_count_52",
+	"oxe_sts_mcu_occ_idc_cell_count_53",
+	"oxe_sts_mcu_occ_idc_cell_count_54",
+	"oxe_sts_mcu_occ_idc_cell_count_55",
+	"oxe_sts_mcu_occ_idc_cell_count_56",
+	"oxe_sts_mcu_occ_idc_cell_count_57",
+	"oxe_sts_mcu_occ_idc_cell_count_58",
+	"oxe_sts_mcu_occ_idc_cell_count_59",
+	"oxe_sts_mcu_occ_idc_cell_count_60",
+	"oxe_sts_mcu_occ_idc_cell_count_61",
+	"oxe_sts_mcu_occ_idc_cell_count_62",
+	"oxe_sts_mcu_occ_idc_cell_count_63",
+	"oxe_sts_mcu_occ_idc_cell_count_64",
+	"oxe_sts_mcu_occ_idc_cell_count_65",
+	"oxe_sts_mcu_occ_idc_cell_count_66",
+	"oxe_sts_mcu_occ_idc_cell_count_67",
+	"oxe_sts_mcu_occ_idc_cell_count_68",
+	"oxe_sts_mcu_occ_idc_cell_count_69",
+	"oxe_sts_mcu_occ_idc_cell_count_70",
+	"oxe_sts_mcu_occ_idc_cell_count_71",
+	"oxe_sts_mcu_occ_idc_cell_count_72",
+	"oxe_sts_mcu_occ_idc_cell_count_73",
+	"oxe_sts_mcu_occ_idc_cell_count_74",
+	"oxe_sts_mcu_occ_idc_cell_count_75",
+	"oxe_sts_mcu_occ_idc_cell_count_76",
+	"oxe_sts_mcu_occ_idc_cell_count_77",
+	"oxe_sts_mcu_occ_idc_cell_count_78",
+	"oxe_sts_mcu_occ_idc_cell_count_79",
+	"oxe_sts_mcu_occ_idc_cell_count_80",
+	"oxe_sts_mcu_occ_idc_cell_count_81",
+	"oxe_sts_mcu_occ_idc_cell_count_82",
+	"oxe_sts_mcu_occ_idc_cell_count_83",
+	"oxe_sts_mcu_occ_idc_cell_count_84",
+	"oxe_sts_mcu_occ_idc_cell_count_85",
+	"oxe_sts_mcu_occ_idc_cell_count_86",
+	"oxe_sts_mcu_occ_idc_cell_count_87",
+	"oxe_sts_mcu_occ_idc_cell_count_88",
+	"oxe_sts_mcu_occ_idc_cell_count_89",
+	"oxe_sts_mcu_occ_idc_cell_count_90",
+	"oxe_sts_mcu_occ_idc_cell_count_91",
+	"oxe_sts_mcu_occ_idc_cell_count_92",
+	"oxe_sts_mcu_occ_idc_cell_count_93",
+	"oxe_sts_mcu_occ_idc_cell_count_94",
+	"oxe_sts_mcu_occ_idc_cell_count_95",
+	"oxe_sts_mcu_occ_mcu_cell_count_0",
+	"oxe_sts_mcu_occ_mcu_cell_count_1",
+	"oxe_sts_mcu_occ_mcu_cell_count_2",
+	"oxe_sts_mcu_occ_mcu_cell_count_3",
+	"oxe_sts_mcu_occ_mcu_cell_count_4",
+	"oxe_sts_mcu_occ_mcu_cell_count_5",
+	"oxe_sts_mcu_occ_mcu_cell_count_6",
+	"oxe_sts_mcu_occ_mcu_cell_count_7",
+	"oxe_sts_mcu_occ_mcu_cell_count_8",
+	"oxe_sts_mcu_occ_mcu_cell_count_9",
+	"oxe_sts_mcu_occ_mcu_cell_count_10",
+	"oxe_sts_mcu_occ_mcu_cell_count_11",
+	"oxe_sts_mcu_occ_mcu_cell_count_12",
+	"oxe_sts_mcu_occ_mcu_cell_count_13",
+	"oxe_sts_mcu_occ_mcu_cell_count_14",
+	"oxe_sts_mcu_occ_mcu_cell_count_15",
+	"oxe_sts_mcu_occ_mcu_cell_count_16",
+	"oxe_sts_mcu_occ_mcu_cell_count_17",
+	"oxe_sts_mcu_occ_mcu_cell_count_18",
+	"oxe_sts_mcu_occ_mcu_cell_count_19",
+	"oxe_sts_mcu_occ_mcu_cell_count_20",
+	"oxe_sts_mcu_occ_mcu_cell_count_21",
+	"oxe_sts_mcu_occ_mcu_cell_count_22",
+	"oxe_sts_mcu_occ_mcu_cell_count_23",
+	"oxe_sts_mcu_occ_mcu_cell_count_24",
+	"oxe_sts_mcu_occ_mcu_cell_count_25",
+	"oxe_sts_mcu_occ_mcu_cell_count_26",
+	"oxe_sts_mcu_occ_mcu_cell_count_27",
+	"oxe_sts_mcu_occ_mcu_cell_count_28",
+	"oxe_sts_mcu_occ_mcu_cell_count_29",
+	"oxe_sts_mcu_occ_mcu_cell_count_30",
+	"oxe_sts_mcu_occ_mcu_cell_count_31",
+	"oxe_sts_mcu_occ_mcu_cell_count_32",
+	"oxe_sts_mcu_occ_mcu_cell_count_33",
+	"oxe_sts_mcu_occ_mcu_cell_count_34",
+	"oxe_sts_mcu_occ_mcu_cell_count_35",
+	"oxe_sts_mcu_occ_mcu_cell_count_36",
+	"oxe_sts_mcu_occ_mcu_cell_count_37",
+	"oxe_sts_mcu_occ_mcu_cell_count_38",
+	"oxe_sts_mcu_occ_mcu_cell_count_39",
+	"oxe_sts_mcu_occ_mcu_cell_count_40",
+	"oxe_sts_mcu_occ_mcu_cell_count_41",
+	"oxe_sts_mcu_occ_mcu_cell_count_42",
+	"oxe_sts_mcu_occ_mcu_cell_count_43",
+	"oxe_sts_mcu_occ_mcu_cell_count_44",
+	"oxe_sts_mcu_occ_mcu_cell_count_45",
+	"oxe_sts_mcu_occ_mcu_cell_count_46",
+	"oxe_sts_mcu_occ_mcu_cell_count_47",
+	"oxe_sts_mcu_occ_mcu_cell_count_48",
+	"oxe_sts_mcu_occ_mcu_cell_count_49",
+	"oxe_sts_mcu_occ_mcu_cell_count_50",
+	"oxe_sts_mcu_occ_mcu_cell_count_51",
+	"oxe_sts_mcu_occ_mcu_cell_count_52",
+	"oxe_sts_mcu_occ_mcu_cell_count_53",
+	"oxe_sts_mcu_occ_mcu_cell_count_54",
+	"oxe_sts_mcu_occ_mcu_cell_count_55",
+	"oxe_sts_mcu_occ_mcu_cell_count_56",
+	"oxe_sts_mcu_occ_mcu_cell_count_57",
+	"oxe_sts_mcu_occ_mcu_cell_count_58",
+	"oxe_sts_mcu_occ_mcu_cell_count_59",
+	"oxe_sts_mcu_occ_mcu_cell_count_60",
+	"oxe_sts_mcu_occ_mcu_cell_count_61",
+	"oxe_sts_mcu_occ_mcu_cell_count_62",
+	"oxe_sts_mcu_occ_mcu_cell_count_63",
+	"oxe_sts_mcu_occ_mcu_cell_count_64",
+	"oxe_sts_mcu_occ_mcu_cell_count_65",
+	"oxe_sts_mcu_occ_mcu_cell_count_66",
+	"oxe_sts_mcu_occ_mcu_cell_count_67",
+	"oxe_sts_mcu_occ_mcu_cell_count_68",
+	"oxe_sts_mcu_occ_mcu_cell_count_69",
+	"oxe_sts_mcu_occ_mcu_cell_count_70",
+	"oxe_sts_mcu_occ_mcu_cell_count_71",
+	"oxe_sts_mcu_occ_mcu_cell_count_72",
+	"oxe_sts_mcu_occ_mcu_cell_count_73",
+	"oxe_sts_mcu_occ_mcu_cell_count_74",
+	"oxe_sts_mcu_occ_mcu_cell_count_75",
+	"oxe_sts_mcu_occ_mcu_cell_count_76",
+	"oxe_sts_mcu_occ_mcu_cell_count_77",
+	"oxe_sts_mcu_occ_mcu_cell_count_78",
+	"oxe_sts_mcu_occ_mcu_cell_count_79",
+	"oxe_sts_mcu_occ_mcu_cell_count_80",
+	"oxe_sts_mcu_occ_mcu_cell_count_81",
+	"oxe_sts_mcu_occ_mcu_cell_count_82",
+	"oxe_sts_mcu_occ_mcu_cell_count_83",
+	"oxe_sts_mcu_occ_mcu_cell_count_84",
+	"oxe_sts_mcu_occ_mcu_cell_count_85",
+	"oxe_sts_mcu_occ_mcu_cell_count_86",
+	"oxe_sts_mcu_occ_mcu_cell_count_87",
+	"oxe_sts_mcu_occ_mcu_cell_count_88",
+	"oxe_sts_mcu_occ_mcu_cell_count_89",
+	"oxe_sts_mcu_occ_mcu_cell_count_90",
+	"oxe_sts_mcu_occ_mcu_cell_count_91",
+	"oxe_sts_mcu_occ_mcu_cell_count_92",
+	"oxe_sts_mcu_occ_mcu_cell_count_93",
+	"oxe_sts_mcu_occ_mcu_cell_count_94",
+	"oxe_sts_mcu_occ_mcu_cell_count_95",
+	"parbs_rarb_atu_completion_pkts",
+	"parbs_rarb_atu_posted_pkts",
+	"parbs_rarb_cq_completion_pkts",
+	"parbs_rarb_cq_posted_pkts",
+	"parbs_rarb_ee_posted_pkts",
+	"parbs_rarb_ixe_completion_pkts",
+	"parbs_rarb_ixe_posted_pkts",
+	"parbs_rarb_oxe_completion_pkts",
+	"parbs_rarb_pi_completion_pkts",
+	"parbs_rarb_pi_mbe_cnt",
+	"parbs_rarb_pi_posted_pkts",
+	"parbs_rarb_pi_sbe_cnt",
+	"parbs_sts_credits_in_use_tarb_pi_non_posted_credits",
+	"parbs_sts_credits_in_use_tarb_pi_posted_credits",
+	"parbs_tarb_atu_mbe_cnt",
+	"parbs_tarb_atu_non_posted_fifo_mbe",
+	"parbs_tarb_atu_non_posted_fifo_sbe",
+	"parbs_tarb_atu_non_posted_pkts",
+	"parbs_tarb_atu_posted_fifo_mbe",
+	"parbs_tarb_atu_posted_fifo_sbe",
+	"parbs_tarb_atu_posted_pkts",
+	"parbs_tarb_atu_sbe_cnt",
+	"parbs_tarb_cq_mbe_cnt",
+	"parbs_tarb_cq_non_posted_fifo_mbe",
+	"parbs_tarb_cq_non_posted_fifo_sbe",
+	"parbs_tarb_cq_non_posted_pkts",
+	"parbs_tarb_cq_posted_fifo_mbe",
+	"parbs_tarb_cq_posted_fifo_sbe",
+	"parbs_tarb_cq_posted_pkts",
+	"parbs_tarb_cq_sbe_cnt",
+	"parbs_tarb_ee_mbe_cnt",
+	"parbs_tarb_ee_posted_fifo_mbe",
+	"parbs_tarb_ee_posted_fifo_sbe",
+	"parbs_tarb_ee_posted_pkts",
+	"parbs_tarb_ee_sbe_cnt",
+	"parbs_tarb_ixe_mbe_cnt",
+	"parbs_tarb_ixe_non_posted_fifo_mbe",
+	"parbs_tarb_ixe_non_posted_fifo_sbe",
+	"parbs_tarb_ixe_non_posted_pkts",
+	"parbs_tarb_ixe_posted_fifo_mbe",
+	"parbs_tarb_ixe_posted_fifo_sbe",
+	"parbs_tarb_ixe_posted_pkts",
+	"parbs_tarb_ixe_sbe_cnt",
+	"parbs_tarb_oxe_mbe_cnt",
+	"parbs_tarb_oxe_non_posted_fifo_mbe",
+	"parbs_tarb_oxe_non_posted_fifo_sbe",
+	"parbs_tarb_oxe_non_posted_pkts",
+	"parbs_tarb_oxe_sbe_cnt",
+	"parbs_tarb_pi_non_posted_blocked_cnt",
+	"parbs_tarb_pi_non_posted_pkts",
+	"parbs_tarb_pi_posted_blocked_cnt",
+	"parbs_tarb_pi_posted_pkts",
+	"pct_accel_close",
+	"pct_bad_seq_nacks",
+	"pct_clear_close_drop",
+	"pct_clear_sent",
+	"pct_close_rsp_drops",
+	"pct_close_sent",
+	"pct_clr_cls_stalls",
+	"pct_cls_req_bad_seqno_drops",
+	"pct_cls_req_miss_tct",
+	"pct_conn_sct_open",
+	"pct_conn_tct_open",
+	"pct_err_no_matching_mst",
+	"pct_err_no_matching_trs",
+	"pct_eth_packets",
+	"pct_host_access_latency_0",
+	"pct_host_access_latency_1",
+	"pct_host_access_latency_2",
+	"pct_host_access_latency_3",
+	"pct_host_access_latency_4",
+	"pct_host_access_latency_5",
+	"pct_host_access_latency_6",
+	"pct_host_access_latency_7",
+	"pct_host_access_latency_8",
+	"pct_host_access_latency_9",
+	"pct_host_access_latency_10",
+	"pct_host_access_latency_11",
+	"pct_host_access_latency_12",
+	"pct_host_access_latency_13",
+	"pct_host_access_latency_14",
+	"pct_host_access_latency_15",
+	"pct_hrp_responses_received",
+	"pct_hrp_rsp_discard_received",
+	"pct_hrp_rsp_err_received",
+	"pct_mem_cor_err_cntr",
+	"pct_mem_ucor_err_cntr",
+	"pct_mst_hit_on_som",
+	"pct_no_matching_tct",
+	"pct_no_mst_nacks",
+	"pct_no_tct_nacks",
+	"pct_no_trs_nacks",
+	"pct_optip_packets",
+	"pct_pct_cq_notifications",
+	"pct_pct_cq_stalls",
+	"pct_pct_ee_events",
+	"pct_pct_ee_stalls",
+	"pct_pct_hni_flits",
+	"pct_pct_hni_stalls",
+	"pct_pct_mst_cmd0",
+	"pct_pct_mst_cmd1",
+	"pct_pct_mst_stalls0",
+	"pct_pct_mst_stalls1",
+	"pct_prf_mst_status_max_mst_in_use",
+	"pct_prf_mst_status_mst_in_use",
+	"pct_prf_sct_status_max_sct_in_use",
+	"pct_prf_sct_status_sct_in_use",
+	"pct_prf_smt_status_max_smt_in_use",
+	"pct_prf_smt_status_smt_in_use",
+	"pct_prf_spt_status_max_spt_in_use",
+	"pct_prf_spt_status_spt_in_use",
+	"pct_prf_srb_status_max_srb_in_use",
+	"pct_prf_srb_status_srb_in_use",
+	"pct_prf_tct_status_max_tct_in_use",
+	"pct_prf_tct_status_tct_in_use",
+	"pct_prf_trs_status_max_trs_in_use",
+	"pct_prf_trs_status_trs_in_use",
+	"pct_ptls_response",
+	"pct_req_blocked_clearing",
+	"pct_req_blocked_closing",
+	"pct_req_blocked_retry",
+	"pct_req_no_response",
+	"pct_req_ordered",
+	"pct_req_rsp_latency_0",
+	"pct_req_rsp_latency_1",
+	"pct_req_rsp_latency_2",
+	"pct_req_rsp_latency_3",
+	"pct_req_rsp_latency_4",
+	"pct_req_rsp_latency_5",
+	"pct_req_rsp_latency_6",
+	"pct_req_rsp_latency_7",
+	"pct_req_rsp_latency_8",
+	"pct_req_rsp_latency_9",
+	"pct_req_rsp_latency_10",
+	"pct_req_rsp_latency_11",
+	"pct_req_rsp_latency_12",
+	"pct_req_rsp_latency_13",
+	"pct_req_rsp_latency_14",
+	"pct_req_rsp_latency_15",
+	"pct_req_rsp_latency_16",
+	"pct_req_rsp_latency_17",
+	"pct_req_rsp_latency_18",
+	"pct_req_rsp_latency_19",
+	"pct_req_rsp_latency_20",
+	"pct_req_rsp_latency_21",
+	"pct_req_rsp_latency_22",
+	"pct_req_rsp_latency_23",
+	"pct_req_rsp_latency_24",
+	"pct_req_rsp_latency_25",
+	"pct_req_rsp_latency_26",
+	"pct_req_rsp_latency_27",
+	"pct_req_rsp_latency_28",
+	"pct_req_rsp_latency_29",
+	"pct_req_rsp_latency_30",
+	"pct_req_rsp_latency_31",
+	"pct_req_src_error",
+	"pct_req_tct_tmout_drops",
+	"pct_req_unordered",
+	"pct_resource_busy",
+	"pct_responses_received",
+	"pct_retry_mst_get",
+	"pct_retry_srb_requests",
+	"pct_retry_trs_put",
+	"pct_rsp_dropped_cls_try",
+	"pct_rsp_dropped_inactive",
+	"pct_rsp_dropped_timeout",
+	"pct_rsp_dropped_try",
+	"pct_rsp_err_rcvd",
+	"pct_sct_stall_state",
+	"pct_sct_timeouts",
+	"pct_spt_timeouts",
+	"pct_tct_timeouts",
+	"pct_tgt_cls_abort",
+	"pct_trs_hit_on_req",
+	"pct_trs_replay_pend_drops",
+	"pct_trs_rsp_nack_drops",
+	"pi_dmac_axi_rd_requests",
+	"pi_dmac_axi_rd_rsp_decerrs",
+	"pi_dmac_axi_rd_rsp_parerrs",
+	"pi_dmac_axi_rd_rsp_slverrs",
+	"pi_dmac_ce_mwr_tlps",
+	"pi_dmac_desc_cor_errors",
+	"pi_dmac_desc_ucor_errors",
+	"pi_dmac_irqs",
+	"pi_dmac_payload_mwr_tlps",
+	"pi_ipd_cfg_event_cnts_ovf_cnt",
+	"pi_ipd_dbic_dbi_acks",
+	"pi_ipd_dbic_dbi_requests",
+	"pi_ipd_dmac_p_fifo_cor_errors",
+	"pi_ipd_dmac_p_fifo_ucor_errors",
+	"pi_ipd_ipd_trigger_events_0",
+	"pi_ipd_ipd_trigger_events_1",
+	"pi_ipd_msixc_ib_irq_pbas",
+	"pi_ipd_msixc_ib_irqs_discarded",
+	"pi_ipd_msixc_ib_irqs_sent",
+	"pi_ipd_msixc_ib_legacy_irqs_sent",
+	"pi_ipd_msixc_oob_irq_pbas",
+	"pi_ipd_msixc_oob_irqs_discarded",
+	"pi_ipd_msixc_oob_irqs_sent",
+	"pi_ipd_msixc_oob_legacy_irqs_sent",
+	"pi_ipd_msixc_pba_cor_errors",
+	"pi_ipd_msixc_pba_ucor_errors",
+	"pi_ipd_msixc_pti_fifo_cor_errors",
+	"pi_ipd_msixc_pti_fifo_ucor_errors",
+	"pi_ipd_msixc_table_cor_errors",
+	"pi_ipd_msixc_table_ucor_errors",
+	"pi_ipd_pri_rbyp_data_parity_errors",
+	"pi_ipd_pri_rbyp_hdr_parity_errors",
+	"pi_ipd_pri_rbyp_tlps",
+	"pi_ipd_pri_rbyp_tlps_aborted",
+	"pi_ipd_pri_rtrgt_blocked_on_mb",
+	"pi_ipd_pri_rtrgt_blocked_on_rarb",
+	"pi_ipd_pri_rtrgt_data_parity_errors",
+	"pi_ipd_pri_rtrgt_hdr_parity_errors",
+	"pi_ipd_pri_rtrgt_mrd_tlps",
+	"pi_ipd_pri_rtrgt_msg_tlps",
+	"pi_ipd_pri_rtrgt_msgd_tlps",
+	"pi_ipd_pri_rtrgt_mwr_tlps",
+	"pi_ipd_pri_rtrgt_tlps",
+	"pi_ipd_pri_rtrgt_tlps_aborted",
+	"pi_ipd_pti_dbg_blocked_on_nph_crd",
+	"pi_ipd_pti_dbg_blocked_on_pd_crd",
+	"pi_ipd_pti_dbg_blocked_on_ph_crd",
+	"pi_ipd_pti_dbg_blocked_on_tag",
+	"pi_ipd_pti_dbg_xali_non_posted_tlps",
+	"pi_ipd_pti_dbg_xali_posted_tlps",
+	"pi_ipd_pti_dmac_blocked_on_pd_crd",
+	"pi_ipd_pti_dmac_blocked_on_ph_crd",
+	"pi_ipd_pti_dmac_xali_posted_tlps",
+	"pi_ipd_pti_msixc_blocked_on_pd_crd",
+	"pi_ipd_pti_msixc_blocked_on_ph_crd",
+	"pi_ipd_pti_msixc_fifo_cor_errors",
+	"pi_ipd_pti_msixc_fifo_ucor_errors",
+	"pi_ipd_pti_msixc_xali_posted_tlps",
+	"pi_ipd_pti_tarb_blocked_on_npd_crd",
+	"pi_ipd_pti_tarb_blocked_on_nph_crd",
+	"pi_ipd_pti_tarb_blocked_on_pd_crd",
+	"pi_ipd_pti_tarb_blocked_on_ph_crd",
+	"pi_ipd_pti_tarb_blocked_on_tag",
+	"pi_ipd_pti_tarb_cmpl_to",
+	"pi_ipd_pti_tarb_cmpl_to_fifo_cor_errors",
+	"pi_ipd_pti_tarb_cmpl_to_fifo_ucor_errors",
+	"pi_ipd_pti_tarb_np_fifo_cor_errors",
+	"pi_ipd_pti_tarb_np_fifo_ucor_errors",
+	"pi_ipd_pti_tarb_p_fifo_cor_errors",
+	"pi_ipd_pti_tarb_p_fifo_ucor_errors",
+	"pi_ipd_pti_tarb_xali_non_posted_tlps",
+	"pi_ipd_pti_tarb_xali_posted_tlps",
+	"pi_pri_mb_axi_rd_requests",
+	"pi_pri_mb_axi_rd_rsp_decerrs",
+	"pi_pri_mb_axi_rd_rsp_parerrs",
+	"pi_pri_mb_axi_rd_rsp_slverrs",
+	"pi_pri_mb_axi_wr_requests",
+	"pi_pri_mb_axi_wr_rsp_decerrs",
+	"pi_pri_mb_axi_wr_rsp_slverrs",
+	"pi_pri_mb_rtrgt_fifo_cor_errors",
+	"pi_pri_mb_rtrgt_fifo_ucor_errors",
+	"pi_pri_mb_rtrgt_mrd_tlps",
+	"pi_pri_mb_rtrgt_mwr_tlps",
+	"pi_pri_mb_rtrgt_non_posted_tlp_discards",
+	"pi_pri_mb_rtrgt_posted_tlp_discards",
+	"pi_pri_mb_rtrgt_posted_tlp_partial_discards",
+	"pi_pri_mb_rtrgt_tlp_discards",
+	"pi_pri_mb_rtrgt_tlps",
+	"pi_pri_mb_xali_cmpl_ca_tlps",
+	"pi_pri_mb_xali_cmpl_tlps",
+	"pi_pri_mb_xali_cmpl_ur_tlps",
+	"pi_pri_rarb_rbyp_fifo_cor_errors",
+	"pi_pri_rarb_rbyp_fifo_ucor_errors",
+	"pi_pri_rarb_rbyp_tlp_discards",
+	"pi_pri_rarb_rbyp_tlps",
+	"pi_pri_rarb_rtrgt_fifo_cor_errors",
+	"pi_pri_rarb_rtrgt_fifo_ucor_errors",
+	"pi_pri_rarb_rtrgt_msg_tlps",
+	"pi_pri_rarb_rtrgt_msgd_tlps",
+	"pi_pri_rarb_rtrgt_mwr_tlps",
+	"pi_pri_rarb_rtrgt_tlp_discards",
+	"pi_pri_rarb_rtrgt_tlps",
+	"pi_pri_rarb_sriovt_cor_errors",
+	"pi_pri_rarb_sriovt_ucor_errors",
+	"pi_pti_tarb_acxt_cor_errors",
+	"pi_pti_tarb_acxt_ucor_errors",
+	"pi_pti_tarb_amo_pkts",
+	"pi_pti_tarb_data_cor_errors",
+	"pi_pti_tarb_data_ucor_error",
+	"pi_pti_tarb_fetching_amo_pkts",
+	"pi_pti_tarb_flush_pkts",
+	"pi_pti_tarb_hdr_cor_errors",
+	"pi_pti_tarb_hdr_ucor_errors",
+	"pi_pti_tarb_inv_rsp_pkts",
+	"pi_pti_tarb_irq_pkts",
+	"pi_pti_tarb_mrd_pkts",
+	"pi_pti_tarb_mwr_pkts",
+	"pi_pti_tarb_pg_req_pkts",
+	"pi_pti_tarb_pkt_discards",
+	"pi_pti_tarb_pkts",
+	"pi_pti_tarb_rarb_ca_pkts",
+	"pi_pti_tarb_translation_pkts",
+	"rmu_enet_frame_rejected_cntr",
+	"rmu_enet_ptlte_set_ctrl_err_cntr",
+	"rmu_enet_success_cntr",
+	"rmu_mem_cor_err_cntr",
+	"rmu_mem_ucor_err_cntr",
+	"rmu_ptl_invld_dfa_cntr",
+	"rmu_ptl_invld_vni_cntr",
+	"rmu_ptl_no_ptlte_cntr",
+	"rmu_ptl_success_cntr",
+	"tou_cmd_fifo_full_cycles",
+	"tou_cq_tou_num_cmds",
+	"tou_cq_tou_num_stalls",
+	"tou_ct_cmd_counts_0",
+	"tou_ct_cmd_counts_1",
+	"tou_ct_cmd_counts_2",
+	"tou_ct_cmd_counts_3",
+	"tou_ct_cmd_counts_4",
+	"tou_ct_cmd_counts_5",
+	"tou_ct_cmd_counts_6",
+	"tou_ct_cmd_counts_7",
+	"tou_ct_cmd_counts_8",
+	"tou_ct_cmd_counts_9",
+	"tou_ct_cmd_counts_10",
+	"tou_ct_cmd_counts_11",
+	"tou_ct_cmd_counts_12",
+	"tou_ct_cmd_counts_13",
+	"tou_ct_cmd_counts_14",
+	"tou_ct_cmd_counts_15",
+	"tou_fail_cntr",
+	"tou_list_rebuild_cycles",
+	"tou_num_ct_updates",
+	"tou_num_doorbell_writes",
+	"tou_num_list_rebuilds_0",
+	"tou_num_list_rebuilds_1",
+	"tou_num_list_rebuilds_2",
+	"tou_num_list_rebuilds_3",
+	"tou_num_trig_cmds_0",
+	"tou_num_trig_cmds_1",
+	"tou_num_trig_cmds_2",
+	"tou_num_trig_cmds_3",
+	"tou_success_cntr",
+	"tou_tou_oxe_num_flits",
+	"tou_tou_oxe_num_idles",
+	"tou_tou_oxe_num_stalls",
+};
+
+static const uint64_t set_ethtool[] = {
+	CXIDV_TELEM_HNI_RX_OK_IEEE,
+	CXIDV_TELEM_HNI_RX_BAD_IEEE,
+	CXIDV_TELEM_HNI_TX_OK_IEEE,
+	CXIDV_TELEM_HNI_TX_POISONED_IEEE,
+	CXIDV_TELEM_HNI_RX_OK_OPT,
+	CXIDV_TELEM_HNI_RX_BAD_OPT,
+	CXIDV_TELEM_HNI_TX_OK_OPT,
+	CXIDV_TELEM_HNI_TX_POISONED_OPT,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW,
+	CXIDV_TELEM_HNI_PCS_UNCORRECTED_CW,
+	CXIDV_TELEM_HNI_PCS_GOOD_CW,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_0,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_1,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_2,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_3,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_4,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_5,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_6,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_7,
+	CXIDV_TELEM_IXE_RX_UDP_PKT,
+	CXIDV_TELEM_IXE_RX_TCP_PKT,
+	CXIDV_TELEM_IXE_RX_IPV4_PKT,
+	CXIDV_TELEM_IXE_RX_IPV6_PKT,
+	CXIDV_TELEM_IXE_RX_ROCE_PKT,
+	CXIDV_TELEM_IXE_RX_PTL_GEN_PKT,
+	CXIDV_TELEM_IXE_RX_PTL_SML_PKT,
+	CXIDV_TELEM_IXE_RX_PTL_UNRESTRICTED_PKT,
+	CXIDV_TELEM_IXE_RX_PTL_SMALLMSG_PKT,
+	CXIDV_TELEM_IXE_RX_PTL_CONTINUATION_PKT,
+	CXIDV_TELEM_IXE_RX_PTL_RESTRICTED_PKT,
+	CXIDV_TELEM_IXE_RX_PTL_CONNMGMT_PKT,
+	CXIDV_TELEM_IXE_RX_PTL_RESPONSE_PKT,
+	CXIDV_TELEM_IXE_RX_UNRECOGNIZED_PKT,
+	CXIDV_TELEM_IXE_RX_PTL_SML_AMO_PKT,
+	CXIDV_TELEM_IXE_RX_PTL_MSGS,
+	CXIDV_TELEM_IXE_RX_PTL_MULTI_MSGS,
+	CXIDV_TELEM_IXE_RX_PTL_MR_MSGS,
+	CXIDV_TELEM_IXE_RX_PKT_DROP_PCT,
+	CXIDV_TELEM_IXE_RX_PKT_DROP_RMU_NORSP,
+	CXIDV_TELEM_IXE_RX_PKT_DROP_RMU_WRSP,
+	CXIDV_TELEM_IXE_RX_PKT_DROP_IXE_PARSER,
+	CXIDV_TELEM_IXE_RX_PKT_IPV4_OPTIONS,
+	CXIDV_TELEM_IXE_RX_PKT_IPV6_OPTIONS,
+	CXIDV_TELEM_IXE_RX_ETH_SEG,
+	CXIDV_TELEM_IXE_RX_ROCE_SEG,
+	CXIDV_TELEM_IXE_RX_ROCE_SPSEG,
+};
+
+static const uint64_t set_atu[] = {
+	CXIDV_TELEM_ATU_AT_STALL_CCP,
+	CXIDV_TELEM_ATU_AT_STALL_NO_PTID,
+	CXIDV_TELEM_ATU_AT_STALL_NP_CDTS,
+	CXIDV_TELEM_ATU_AT_STALL_TARB_ARB,
+	CXIDV_TELEM_ATU_ATS_DYNAMIC_STATE_CHANGE_CNTR,
+	CXIDV_TELEM_ATU_ATS_INVAL_CNTR,
+	CXIDV_TELEM_ATU_ATS_PRS_ODP_LATENCY_0,
+	CXIDV_TELEM_ATU_ATS_PRS_ODP_LATENCY_1,
+	CXIDV_TELEM_ATU_ATS_PRS_ODP_LATENCY_2,
+	CXIDV_TELEM_ATU_ATS_PRS_ODP_LATENCY_3,
+	CXIDV_TELEM_ATU_ATS_TRANS_ERR,
+	CXIDV_TELEM_ATU_ATS_TRANS_LATENCY_0,
+	CXIDV_TELEM_ATU_ATS_TRANS_LATENCY_1,
+	CXIDV_TELEM_ATU_ATS_TRANS_LATENCY_2,
+	CXIDV_TELEM_ATU_ATS_TRANS_LATENCY_3,
+	CXIDV_TELEM_ATU_ATUCQ_INVAL_CNTR,
+	CXIDV_TELEM_ATU_CACHE_EVICTIONS,
+	CXIDV_TELEM_ATU_CACHE_HIT_BASE_PAGE_SIZE_0,
+	CXIDV_TELEM_ATU_CACHE_HIT_BASE_PAGE_SIZE_1,
+	CXIDV_TELEM_ATU_CACHE_HIT_BASE_PAGE_SIZE_2,
+	CXIDV_TELEM_ATU_CACHE_HIT_BASE_PAGE_SIZE_3,
+	CXIDV_TELEM_ATU_CACHE_HIT_DERIVATIVE1_PAGE_SIZE_0,
+	CXIDV_TELEM_ATU_CACHE_HIT_DERIVATIVE1_PAGE_SIZE_1,
+	CXIDV_TELEM_ATU_CACHE_HIT_DERIVATIVE1_PAGE_SIZE_2,
+	CXIDV_TELEM_ATU_CACHE_HIT_DERIVATIVE1_PAGE_SIZE_3,
+	CXIDV_TELEM_ATU_CACHE_HIT_DERIVATIVE2_PAGE_SIZE_0,
+	CXIDV_TELEM_ATU_CACHE_HIT_DERIVATIVE2_PAGE_SIZE_1,
+	CXIDV_TELEM_ATU_CACHE_HIT_DERIVATIVE2_PAGE_SIZE_2,
+	CXIDV_TELEM_ATU_CACHE_HIT_DERIVATIVE2_PAGE_SIZE_3,
+	CXIDV_TELEM_ATU_CACHE_MISS_0,
+	CXIDV_TELEM_ATU_CACHE_MISS_1,
+	CXIDV_TELEM_ATU_CACHE_MISS_2,
+	CXIDV_TELEM_ATU_CACHE_MISS_3,
+	CXIDV_TELEM_ATU_CACHE_MISS_EE,
+	CXIDV_TELEM_ATU_CACHE_MISS_IXE,
+	CXIDV_TELEM_ATU_CACHE_MISS_OXE,
+	CXIDV_TELEM_ATU_CLIENT_REQ_EE,
+	CXIDV_TELEM_ATU_CLIENT_REQ_IXE,
+	CXIDV_TELEM_ATU_CLIENT_REQ_OXE,
+	CXIDV_TELEM_ATU_CLIENT_RSP_NOT_OK_0,
+	CXIDV_TELEM_ATU_CLIENT_RSP_NOT_OK_1,
+	CXIDV_TELEM_ATU_CLIENT_RSP_NOT_OK_2,
+	CXIDV_TELEM_ATU_CLIENT_RSP_NOT_OK_3,
+	CXIDV_TELEM_ATU_FILTERED_REQUESTS,
+	CXIDV_TELEM_ATU_IMPLICIT_ATS_EN_INVAL_CNTR,
+	CXIDV_TELEM_ATU_IMPLICIT_FLR_INVAL_CNTR,
+	CXIDV_TELEM_ATU_INVAL_STALL_ARB,
+	CXIDV_TELEM_ATU_INVAL_STALL_CMPL_WAIT,
+	CXIDV_TELEM_ATU_MEM_COR_ERR_CNTR,
+	CXIDV_TELEM_ATU_MEM_UCOR_ERR_CNTR,
+	CXIDV_TELEM_ATU_NIC_PRI_ODP_LATENCY_0,
+	CXIDV_TELEM_ATU_NIC_PRI_ODP_LATENCY_1,
+	CXIDV_TELEM_ATU_NIC_PRI_ODP_LATENCY_2,
+	CXIDV_TELEM_ATU_NIC_PRI_ODP_LATENCY_3,
+	CXIDV_TELEM_ATU_NTA_TRANS_LATENCY_0,
+	CXIDV_TELEM_ATU_NTA_TRANS_LATENCY_1,
+	CXIDV_TELEM_ATU_NTA_TRANS_LATENCY_2,
+	CXIDV_TELEM_ATU_NTA_TRANS_LATENCY_3,
+	CXIDV_TELEM_ATU_ODP_REQUESTS_0,
+	CXIDV_TELEM_ATU_ODP_REQUESTS_1,
+	CXIDV_TELEM_ATU_ODP_REQUESTS_2,
+	CXIDV_TELEM_ATU_ODP_REQUESTS_3,
+	CXIDV_TELEM_ATU_PCIE_ERR_POISONED,
+	CXIDV_TELEM_ATU_PCIE_UNSUCCESS_CMPL,
+};
+
+static const uint64_t set_cq[] = {
+	CXIDV_TELEM_CQ_CFG_EVENT_CNTS_OVF_CNT,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_0,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_1,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_2,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_3,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_4,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_5,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_6,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_7,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_8,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_9,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_10,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_11,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_12,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_13,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_14,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_15,
+	CXIDV_TELEM_CQ_CQ_OXE_NUM_FLITS,
+	CXIDV_TELEM_CQ_CQ_OXE_NUM_IDLES,
+	CXIDV_TELEM_CQ_CQ_OXE_NUM_STALLS,
+	CXIDV_TELEM_CQ_CQ_TOU_NUM_FLITS,
+	CXIDV_TELEM_CQ_CQ_TOU_NUM_IDLES,
+	CXIDV_TELEM_CQ_CQ_TOU_NUM_STALLS,
+	CXIDV_TELEM_CQ_CYCLES_BLOCKED_0,
+	CXIDV_TELEM_CQ_CYCLES_BLOCKED_1,
+	CXIDV_TELEM_CQ_CYCLES_BLOCKED_2,
+	CXIDV_TELEM_CQ_CYCLES_BLOCKED_3,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_0,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_1,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_2,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_3,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_4,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_5,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_6,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_7,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_8,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_9,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_10,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_11,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_12,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_13,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_14,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_15,
+	CXIDV_TELEM_CQ_FAIL_TGT_CNTR,
+	CXIDV_TELEM_CQ_FAIL_TX_CNTR,
+	CXIDV_TELEM_CQ_MEM_COR_ERR_CNTR,
+	CXIDV_TELEM_CQ_MEM_UCOR_ERR_CNTR,
+	CXIDV_TELEM_CQ_NUM_CQ_CMDS_0,
+	CXIDV_TELEM_CQ_NUM_CQ_CMDS_1,
+	CXIDV_TELEM_CQ_NUM_CQ_CMDS_2,
+	CXIDV_TELEM_CQ_NUM_CQ_CMDS_3,
+	CXIDV_TELEM_CQ_NUM_DMA_CMDS_0,
+	CXIDV_TELEM_CQ_NUM_DMA_CMDS_1,
+	CXIDV_TELEM_CQ_NUM_DMA_CMDS_2,
+	CXIDV_TELEM_CQ_NUM_DMA_CMDS_3,
+	CXIDV_TELEM_CQ_NUM_IDC_CMDS_0,
+	CXIDV_TELEM_CQ_NUM_IDC_CMDS_1,
+	CXIDV_TELEM_CQ_NUM_IDC_CMDS_2,
+	CXIDV_TELEM_CQ_NUM_IDC_CMDS_3,
+	CXIDV_TELEM_CQ_NUM_LL_CMDS_0,
+	CXIDV_TELEM_CQ_NUM_LL_CMDS_1,
+	CXIDV_TELEM_CQ_NUM_LL_CMDS_2,
+	CXIDV_TELEM_CQ_NUM_LL_CMDS_3,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_RECEIVED_0,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_RECEIVED_1,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_RECEIVED_2,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_RECEIVED_3,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_REJECTED_0,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_REJECTED_1,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_REJECTED_2,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_REJECTED_3,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_SPLIT_0,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_SPLIT_1,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_SPLIT_2,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_SPLIT_3,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_SUCCESSFUL_0,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_SUCCESSFUL_1,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_SUCCESSFUL_2,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_SUCCESSFUL_3,
+	CXIDV_TELEM_CQ_NUM_TGQ_CMD_READS_0,
+	CXIDV_TELEM_CQ_NUM_TGQ_CMD_READS_1,
+	CXIDV_TELEM_CQ_NUM_TGQ_CMD_READS_2,
+	CXIDV_TELEM_CQ_NUM_TGQ_CMD_READS_3,
+	CXIDV_TELEM_CQ_NUM_TGT_CMD_ARG_ERRORS,
+	CXIDV_TELEM_CQ_NUM_TGT_CMD_PERM_ERRORS,
+	CXIDV_TELEM_CQ_NUM_TGT_CMDS_0,
+	CXIDV_TELEM_CQ_NUM_TGT_CMDS_1,
+	CXIDV_TELEM_CQ_NUM_TGT_CMDS_2,
+	CXIDV_TELEM_CQ_NUM_TGT_CMDS_3,
+	CXIDV_TELEM_CQ_NUM_TOU_CMD_READS_0,
+	CXIDV_TELEM_CQ_NUM_TOU_CMD_READS_1,
+	CXIDV_TELEM_CQ_NUM_TOU_CMD_READS_2,
+	CXIDV_TELEM_CQ_NUM_TOU_CMD_READS_3,
+	CXIDV_TELEM_CQ_NUM_TX_CMD_ALIGN_ERRORS,
+	CXIDV_TELEM_CQ_NUM_TX_CMD_ARG_ERRORS,
+	CXIDV_TELEM_CQ_NUM_TX_CMD_OP_ERRORS,
+	CXIDV_TELEM_CQ_NUM_TX_CMD_PERM_ERRORS,
+	CXIDV_TELEM_CQ_NUM_TXQ_CMD_READS_0,
+	CXIDV_TELEM_CQ_NUM_TXQ_CMD_READS_1,
+	CXIDV_TELEM_CQ_NUM_TXQ_CMD_READS_2,
+	CXIDV_TELEM_CQ_NUM_TXQ_CMD_READS_3,
+	CXIDV_TELEM_CQ_RARB_ERR_CNTR,
+	CXIDV_TELEM_CQ_RARB_LL_ERR_CNTR,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_EE_EVENT_CREDITS,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_FQ_SH_CREDITS,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_FQ_TOT_CREDITS,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_LPE_CMD_CREDITS,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_LPE_RCV_FIFO_CREDITS,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_PREFETCH_TOU_CREDITS,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_TARB_NP_CREDITS,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_TARB_P_CREDITS,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_TGQ_CMD_FAIL_EVENT_CREDITS,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_TOU_CMD_FAIL_EVENT_CREDITS,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_TOU_EVENT_CREDITS,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_TOU_FQ_CREDITS,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_TOU_WB_CREDITS,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_TXQ_CMD_FAIL_EVENT_CREDITS,
+	CXIDV_TELEM_CQ_STS_DMA_PAYLOAD_DATA_0,
+	CXIDV_TELEM_CQ_STS_DMA_PAYLOAD_DATA_1,
+	CXIDV_TELEM_CQ_STS_DMA_PAYLOAD_DATA_2,
+	CXIDV_TELEM_CQ_STS_DMA_PAYLOAD_DATA_3,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_0,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_1,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_2,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_3,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_4,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_5,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_6,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_7,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_8,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_9,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_10,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_11,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_12,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_13,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_14,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_15,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_16,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_17,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_18,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_19,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_20,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_21,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_22,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_23,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_24,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_25,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_26,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_27,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_28,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_29,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_30,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_31,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_32,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_33,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_34,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_35,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_36,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_37,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_38,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_39,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_40,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_41,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_42,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_43,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_44,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_45,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_46,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_47,
+	CXIDV_TELEM_CQ_STS_IDC_PAYLOAD_DATA_0,
+	CXIDV_TELEM_CQ_STS_IDC_PAYLOAD_DATA_1,
+	CXIDV_TELEM_CQ_STS_IDC_PAYLOAD_DATA_2,
+	CXIDV_TELEM_CQ_STS_IDC_PAYLOAD_DATA_3,
+	CXIDV_TELEM_CQ_STS_LL_DMA_PAYLOAD_DATA_0,
+	CXIDV_TELEM_CQ_STS_LL_DMA_PAYLOAD_DATA_1,
+	CXIDV_TELEM_CQ_STS_LL_DMA_PAYLOAD_DATA_2,
+	CXIDV_TELEM_CQ_STS_LL_DMA_PAYLOAD_DATA_3,
+	CXIDV_TELEM_CQ_STS_LL_IDC_PAYLOAD_DATA_0,
+	CXIDV_TELEM_CQ_STS_LL_IDC_PAYLOAD_DATA_1,
+	CXIDV_TELEM_CQ_STS_LL_IDC_PAYLOAD_DATA_2,
+	CXIDV_TELEM_CQ_STS_LL_IDC_PAYLOAD_DATA_3,
+	CXIDV_TELEM_CQ_STS_TLE_IN_USE_0,
+	CXIDV_TELEM_CQ_STS_TLE_IN_USE_1,
+	CXIDV_TELEM_CQ_STS_TLE_IN_USE_2,
+	CXIDV_TELEM_CQ_STS_TLE_IN_USE_3,
+	CXIDV_TELEM_CQ_STS_TOU_PAYLOAD_DATA_0,
+	CXIDV_TELEM_CQ_STS_TOU_PAYLOAD_DATA_1,
+	CXIDV_TELEM_CQ_STS_TOU_PAYLOAD_DATA_2,
+	CXIDV_TELEM_CQ_STS_TOU_PAYLOAD_DATA_3,
+	CXIDV_TELEM_CQ_SUCCESS_TGT_CNTR,
+	CXIDV_TELEM_CQ_SUCCESS_TX_CNTR,
+	CXIDV_TELEM_CQ_TGT_WAITING_ON_READ_0,
+	CXIDV_TELEM_CQ_TGT_WAITING_ON_READ_1,
+	CXIDV_TELEM_CQ_TGT_WAITING_ON_READ_2,
+	CXIDV_TELEM_CQ_TGT_WAITING_ON_READ_3,
+	CXIDV_TELEM_CQ_TX_WAITING_ON_READ_0,
+	CXIDV_TELEM_CQ_TX_WAITING_ON_READ_1,
+	CXIDV_TELEM_CQ_TX_WAITING_ON_READ_2,
+	CXIDV_TELEM_CQ_TX_WAITING_ON_READ_3,
+	CXIDV_TELEM_CQ_WR_PTR_UPDT_ERR_CNTR,
+};
+
+static const uint64_t set_ee[] = {
+	CXIDV_TELEM_EE_ADDR_TRANS_PREFETCH_CNTR_0,
+	CXIDV_TELEM_EE_ADDR_TRANS_PREFETCH_CNTR_1,
+	CXIDV_TELEM_EE_ADDR_TRANS_PREFETCH_CNTR_2,
+	CXIDV_TELEM_EE_ADDR_TRANS_PREFETCH_CNTR_3,
+	CXIDV_TELEM_EE_ADDR_TRANS_REQ_CNTR,
+	CXIDV_TELEM_EE_CBS_WRITTEN_CNTR_0,
+	CXIDV_TELEM_EE_CBS_WRITTEN_CNTR_1,
+	CXIDV_TELEM_EE_CBS_WRITTEN_CNTR_2,
+	CXIDV_TELEM_EE_CBS_WRITTEN_CNTR_3,
+	CXIDV_TELEM_EE_CE_ARB_OUT_EVENT_CNTR,
+	CXIDV_TELEM_EE_CE_ARB_OUT_STALL_CNTR,
+	CXIDV_TELEM_EE_CQ_EVENT_REQ_CNTR,
+	CXIDV_TELEM_EE_CQ_FE_CNTR,
+	CXIDV_TELEM_EE_CQ_FE_STALL_CNTR,
+	CXIDV_TELEM_EE_DEFERRED_EQ_SWITCH_CNTR_0,
+	CXIDV_TELEM_EE_DEFERRED_EQ_SWITCH_CNTR_1,
+	CXIDV_TELEM_EE_DEFERRED_EQ_SWITCH_CNTR_2,
+	CXIDV_TELEM_EE_DEFERRED_EQ_SWITCH_CNTR_3,
+	CXIDV_TELEM_EE_EQ_BUFFER_SWITCH_CNTR_0,
+	CXIDV_TELEM_EE_EQ_BUFFER_SWITCH_CNTR_1,
+	CXIDV_TELEM_EE_EQ_BUFFER_SWITCH_CNTR_2,
+	CXIDV_TELEM_EE_EQ_BUFFER_SWITCH_CNTR_3,
+	CXIDV_TELEM_EE_EQ_DSABLD_EVENT_ERR_CNTR,
+	CXIDV_TELEM_EE_EQ_DSABLD_LPEQ_ERR_CNTR,
+	CXIDV_TELEM_EE_EQ_DSABLD_SWS_ERR_CNTR,
+	CXIDV_TELEM_EE_EQ_RSRVN_UFLW_ERR_CNTR,
+	CXIDV_TELEM_EE_EQ_STATE_UCOR_ERR_CNTR,
+	CXIDV_TELEM_EE_EQ_STATUS_UPDATE_CNTR_0,
+	CXIDV_TELEM_EE_EQ_STATUS_UPDATE_CNTR_1,
+	CXIDV_TELEM_EE_EQ_STATUS_UPDATE_CNTR_2,
+	CXIDV_TELEM_EE_EQ_STATUS_UPDATE_CNTR_3,
+	CXIDV_TELEM_EE_EQ_SW_STATE_WR_CNTR_0,
+	CXIDV_TELEM_EE_EQ_SW_STATE_WR_CNTR_1,
+	CXIDV_TELEM_EE_EQ_SW_STATE_WR_CNTR_2,
+	CXIDV_TELEM_EE_EQ_SW_STATE_WR_CNTR_3,
+	CXIDV_TELEM_EE_EQS_ARB_OUT_REQ_CNTR,
+	CXIDV_TELEM_EE_EQS_CSR_REQ_CNTR,
+	CXIDV_TELEM_EE_EQS_CSR_STALL_CNTR,
+	CXIDV_TELEM_EE_EQS_EVENT_REQ_CNTR,
+	CXIDV_TELEM_EE_EQS_EVENT_STALL_CNTR,
+	CXIDV_TELEM_EE_EQS_EXPIRED_CB_REQ_CNTR,
+	CXIDV_TELEM_EE_EQS_EXPIRED_CB_STALL_CNTR,
+	CXIDV_TELEM_EE_EQS_FREE_CB_STALL_CNTR,
+	CXIDV_TELEM_EE_EQS_HWS_INIT_REQ_CNTR,
+	CXIDV_TELEM_EE_EQS_HWS_INIT_STALL_CNTR,
+	CXIDV_TELEM_EE_EQS_LPE_QUERY_REQ_CNTR,
+	CXIDV_TELEM_EE_EQS_STS_UPDT_REQ_CNTR,
+	CXIDV_TELEM_EE_EQS_STS_UPDT_STALL_CNTR,
+	CXIDV_TELEM_EE_EQS_SWS_WR_REQ_CNTR,
+	CXIDV_TELEM_EE_EQS_SWS_WR_STALL_CNTR,
+	CXIDV_TELEM_EE_EVENT_ACK_CNTR,
+	CXIDV_TELEM_EE_EVENT_ATOMIC_CNTR,
+	CXIDV_TELEM_EE_EVENT_ATOMIC_OVERFLOW_CNTR,
+	CXIDV_TELEM_EE_EVENT_COMMAND_FAILURE_CNTR,
+	CXIDV_TELEM_EE_EVENT_EQ_SWITCH_CNTR,
+	CXIDV_TELEM_EE_EVENT_ERROR_CNTR,
+	CXIDV_TELEM_EE_EVENT_ETHERNET_CNTR,
+	CXIDV_TELEM_EE_EVENT_ETHERNET_FGFC_CNTR,
+	CXIDV_TELEM_EE_EVENT_FETCH_ATOMIC_CNTR,
+	CXIDV_TELEM_EE_EVENT_FETCH_ATOMIC_OVERFLOW_CNTR,
+	CXIDV_TELEM_EE_EVENT_GET_CNTR,
+	CXIDV_TELEM_EE_EVENT_GET_OVERFLOW_CNTR,
+	CXIDV_TELEM_EE_EVENT_LINK_CNTR,
+	CXIDV_TELEM_EE_EVENT_MATCH_CNTR,
+	CXIDV_TELEM_EE_EVENT_NULL_EVENT_CNTR,
+	CXIDV_TELEM_EE_EVENT_PCT_CNTR,
+	CXIDV_TELEM_EE_EVENT_PUT_CNTR,
+	CXIDV_TELEM_EE_EVENT_PUT_OVERFLOW_CNTR,
+	CXIDV_TELEM_EE_EVENT_RENDEZVOUS_CNTR,
+	CXIDV_TELEM_EE_EVENT_REPLY_CNTR,
+	CXIDV_TELEM_EE_EVENT_SEARCH_CNTR,
+	CXIDV_TELEM_EE_EVENT_SEND_CNTR,
+	CXIDV_TELEM_EE_EVENT_STATE_CHANGE_CNTR,
+	CXIDV_TELEM_EE_EVENT_TIMESTAMP_CNTR,
+	CXIDV_TELEM_EE_EVENT_TRIGGERED_OP_CNTR,
+	CXIDV_TELEM_EE_EVENT_UNLINK_CNTR,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_FC_SC_CNTR_0,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_FC_SC_CNTR_1,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_FC_SC_CNTR_2,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_FC_SC_CNTR_3,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_ORDINARY_CNTR_0,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_ORDINARY_CNTR_1,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_ORDINARY_CNTR_2,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_ORDINARY_CNTR_3,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_RSRVN_CNTR_0,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_RSRVN_CNTR_1,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_RSRVN_CNTR_2,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_RSRVN_CNTR_3,
+	CXIDV_TELEM_EE_EVENTS_ENQUEUED_CNTR_0,
+	CXIDV_TELEM_EE_EVENTS_ENQUEUED_CNTR_1,
+	CXIDV_TELEM_EE_EVENTS_ENQUEUED_CNTR_2,
+	CXIDV_TELEM_EE_EVENTS_ENQUEUED_CNTR_3,
+	CXIDV_TELEM_EE_EXPIRED_CBS_WRITTEN_CNTR_0,
+	CXIDV_TELEM_EE_EXPIRED_CBS_WRITTEN_CNTR_1,
+	CXIDV_TELEM_EE_EXPIRED_CBS_WRITTEN_CNTR_2,
+	CXIDV_TELEM_EE_EXPIRED_CBS_WRITTEN_CNTR_3,
+	CXIDV_TELEM_EE_FE_ARB_OUT_EVENT_CNTR,
+	CXIDV_TELEM_EE_FE_ARB_OUT_STALL_CNTR,
+	CXIDV_TELEM_EE_HNI_EVENT_REQ_CNTR,
+	CXIDV_TELEM_EE_HNI_FE_CNTR,
+	CXIDV_TELEM_EE_HNI_FE_STALL_CNTR,
+	CXIDV_TELEM_EE_IXE_CE_CNTR,
+	CXIDV_TELEM_EE_IXE_CE_STALL_CNTR,
+	CXIDV_TELEM_EE_IXE_DD_CNTR,
+	CXIDV_TELEM_EE_IXE_EVENT_REQ_CNTR,
+	CXIDV_TELEM_EE_IXE_FE_CNTR,
+	CXIDV_TELEM_EE_IXE_FE_STALL_CNTR,
+	CXIDV_TELEM_EE_LPE_CE_CNTR,
+	CXIDV_TELEM_EE_LPE_CE_STALL_CNTR,
+	CXIDV_TELEM_EE_LPE_DD_CNTR,
+	CXIDV_TELEM_EE_LPE_EVENT_REQ_CNTR,
+	CXIDV_TELEM_EE_LPE_FE_CNTR,
+	CXIDV_TELEM_EE_LPE_FE_STALL_CNTR,
+	CXIDV_TELEM_EE_LPE_QUERY_EQ_NONE_CNTR,
+	CXIDV_TELEM_EE_MEM_COR_ERR_CNTR,
+	CXIDV_TELEM_EE_MEM_UCOR_ERR_CNTR,
+	CXIDV_TELEM_EE_MST_CE_CNTR,
+	CXIDV_TELEM_EE_MST_CE_STALL_CNTR,
+	CXIDV_TELEM_EE_MST_DD_CNTR,
+	CXIDV_TELEM_EE_MST_EVENT_REQ_CNTR,
+	CXIDV_TELEM_EE_MST_FE_CNTR,
+	CXIDV_TELEM_EE_MST_FE_STALL_CNTR,
+	CXIDV_TELEM_EE_PARTIAL_CBS_WRITTEN_CNTR_0,
+	CXIDV_TELEM_EE_PARTIAL_CBS_WRITTEN_CNTR_1,
+	CXIDV_TELEM_EE_PARTIAL_CBS_WRITTEN_CNTR_2,
+	CXIDV_TELEM_EE_PARTIAL_CBS_WRITTEN_CNTR_3,
+	CXIDV_TELEM_EE_PCT_CE_CNTR,
+	CXIDV_TELEM_EE_PCT_CE_STALL_CNTR,
+	CXIDV_TELEM_EE_PCT_DD_CNTR,
+	CXIDV_TELEM_EE_PCT_EVENT_REQ_CNTR,
+	CXIDV_TELEM_EE_PCT_FE_CNTR,
+	CXIDV_TELEM_EE_PCT_FE_STALL_CNTR,
+	CXIDV_TELEM_EE_RARB_HW_ERR_CNTR,
+	CXIDV_TELEM_EE_RARB_SW_ERR_CNTR,
+	CXIDV_TELEM_EE_STS_ECBS_IN_USE_ECBS_IN_USE,
+	CXIDV_TELEM_EE_STS_ECBS_IN_USE_MAX_ECBS_IN_USE,
+	CXIDV_TELEM_EE_TARB_ERR_CNTR,
+	CXIDV_TELEM_EE_TARB_IRQ_REQ_CNTR,
+	CXIDV_TELEM_EE_TARB_STALL_CNTR,
+	CXIDV_TELEM_EE_TARB_WR_REQ_CNTR,
+	CXIDV_TELEM_EE_TS_FE_CNTR,
+	CXIDV_TELEM_EE_TS_FE_STALL_CNTR,
+	CXIDV_TELEM_EE_UNXPCTD_TRNSLTN_RSP_ERR_CNTR,
+};
+
+static const uint64_t set_hni[] = {
+	CXIDV_TELEM_HNI_CFG_EVENT_CNTS_OVF_CNT,
+	CXIDV_TELEM_HNI_COR_ECC_ERR_CNTR,
+	CXIDV_TELEM_HNI_DISCARD_CNTR_0,
+	CXIDV_TELEM_HNI_DISCARD_CNTR_1,
+	CXIDV_TELEM_HNI_DISCARD_CNTR_2,
+	CXIDV_TELEM_HNI_DISCARD_CNTR_3,
+	CXIDV_TELEM_HNI_DISCARD_CNTR_4,
+	CXIDV_TELEM_HNI_DISCARD_CNTR_5,
+	CXIDV_TELEM_HNI_DISCARD_CNTR_6,
+	CXIDV_TELEM_HNI_DISCARD_CNTR_7,
+	CXIDV_TELEM_HNI_FGFC_DISCARD,
+	CXIDV_TELEM_HNI_FGFC_EVENT_XOFF,
+	CXIDV_TELEM_HNI_FGFC_EVENT_XON,
+	CXIDV_TELEM_HNI_FGFC_IPV4,
+	CXIDV_TELEM_HNI_FGFC_IPV6,
+	CXIDV_TELEM_HNI_FGFC_L2,
+	CXIDV_TELEM_HNI_FGFC_MATCH,
+	CXIDV_TELEM_HNI_FGFC_PORT,
+	CXIDV_TELEM_HNI_HRP_ACK,
+	CXIDV_TELEM_HNI_HRP_RESP,
+	CXIDV_TELEM_HNI_LLR_RX_ACK_CTL_OS,
+	CXIDV_TELEM_HNI_LLR_RX_ACK_NACK_ERROR,
+	CXIDV_TELEM_HNI_LLR_RX_ACK_NACK_SEQ_ERR,
+	CXIDV_TELEM_HNI_LLR_RX_BAD_CTL_FR,
+	CXIDV_TELEM_HNI_LLR_RX_BAD_LOSSLESS,
+	CXIDV_TELEM_HNI_LLR_RX_BAD_LOSSY,
+	CXIDV_TELEM_HNI_LLR_RX_DUPLICATE_SEQ,
+	CXIDV_TELEM_HNI_LLR_RX_EXPECTED_SEQ_BAD,
+	CXIDV_TELEM_HNI_LLR_RX_EXPECTED_SEQ_GOOD,
+	CXIDV_TELEM_HNI_LLR_RX_EXPECTED_SEQ_POISONED,
+	CXIDV_TELEM_HNI_LLR_RX_INIT_CTL_OS,
+	CXIDV_TELEM_HNI_LLR_RX_INIT_ECHO_CTL_OS,
+	CXIDV_TELEM_HNI_LLR_RX_LOOP_TIME_REQ_CTL_FR,
+	CXIDV_TELEM_HNI_LLR_RX_LOOP_TIME_RSP_CTL_FR,
+	CXIDV_TELEM_HNI_LLR_RX_NACK_CTL_OS,
+	CXIDV_TELEM_HNI_LLR_RX_OK_LOSSLESS,
+	CXIDV_TELEM_HNI_LLR_RX_OK_LOSSY,
+	CXIDV_TELEM_HNI_LLR_RX_POISONED_LOSSLESS,
+	CXIDV_TELEM_HNI_LLR_RX_POISONED_LOSSY,
+	CXIDV_TELEM_HNI_LLR_RX_REPLAY_EVENT,
+	CXIDV_TELEM_HNI_LLR_RX_UNEXPECTED_SEQ,
+	CXIDV_TELEM_HNI_LLR_TX_ACK_CTL_OS,
+	CXIDV_TELEM_HNI_LLR_TX_BAD_LOSSLESS,
+	CXIDV_TELEM_HNI_LLR_TX_BAD_LOSSLESS_RPT,
+	CXIDV_TELEM_HNI_LLR_TX_BAD_LOSSY,
+	CXIDV_TELEM_HNI_LLR_TX_DISCARD,
+	CXIDV_TELEM_HNI_LLR_TX_INIT_CTL_OS,
+	CXIDV_TELEM_HNI_LLR_TX_INIT_ECHO_CTL_OS,
+	CXIDV_TELEM_HNI_LLR_TX_LLR_BLOCKED,
+	CXIDV_TELEM_HNI_LLR_TX_LLR_UNBLOCKED,
+	CXIDV_TELEM_HNI_LLR_TX_LOOP_TIME_REQ_CTL_FR,
+	CXIDV_TELEM_HNI_LLR_TX_LOOP_TIME_RSP_CTL_FR,
+	CXIDV_TELEM_HNI_LLR_TX_NACK_CTL_OS,
+	CXIDV_TELEM_HNI_LLR_TX_OK_BYPASS,
+	CXIDV_TELEM_HNI_LLR_TX_OK_LOSSLESS,
+	CXIDV_TELEM_HNI_LLR_TX_OK_LOSSLESS_RPT,
+	CXIDV_TELEM_HNI_LLR_TX_OK_LOSSY,
+	CXIDV_TELEM_HNI_LLR_TX_POISONED_LOSSLESS,
+	CXIDV_TELEM_HNI_LLR_TX_POISONED_LOSSLESS_RPT,
+	CXIDV_TELEM_HNI_LLR_TX_POISONED_LOSSY,
+	CXIDV_TELEM_HNI_LLR_TX_REPLAY_EVENT,
+	CXIDV_TELEM_HNI_MAC_RX_FRAGMENT,
+	CXIDV_TELEM_HNI_MAC_RX_ILLEGAL_SIZE,
+	CXIDV_TELEM_HNI_MAC_RX_PREAMBLE_ERROR,
+	CXIDV_TELEM_HNI_MAC_TX_IFG_ADJUSTMENT_SYNC,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_RECV_BY_TC_0,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_RECV_BY_TC_1,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_RECV_BY_TC_2,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_RECV_BY_TC_3,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_RECV_BY_TC_4,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_RECV_BY_TC_5,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_RECV_BY_TC_6,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_RECV_BY_TC_7,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_SENT_BY_TC_0,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_SENT_BY_TC_1,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_SENT_BY_TC_2,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_SENT_BY_TC_3,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_SENT_BY_TC_4,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_SENT_BY_TC_5,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_SENT_BY_TC_6,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_SENT_BY_TC_7,
+	CXIDV_TELEM_HNI_PAUSE_RECV_0,
+	CXIDV_TELEM_HNI_PAUSE_RECV_1,
+	CXIDV_TELEM_HNI_PAUSE_RECV_2,
+	CXIDV_TELEM_HNI_PAUSE_RECV_3,
+	CXIDV_TELEM_HNI_PAUSE_RECV_4,
+	CXIDV_TELEM_HNI_PAUSE_RECV_5,
+	CXIDV_TELEM_HNI_PAUSE_RECV_6,
+	CXIDV_TELEM_HNI_PAUSE_RECV_7,
+	CXIDV_TELEM_HNI_PAUSE_REFRESH,
+	CXIDV_TELEM_HNI_PAUSE_SENT,
+	CXIDV_TELEM_HNI_PAUSE_XOFF_SENT_0,
+	CXIDV_TELEM_HNI_PAUSE_XOFF_SENT_1,
+	CXIDV_TELEM_HNI_PAUSE_XOFF_SENT_2,
+	CXIDV_TELEM_HNI_PAUSE_XOFF_SENT_3,
+	CXIDV_TELEM_HNI_PAUSE_XOFF_SENT_4,
+	CXIDV_TELEM_HNI_PAUSE_XOFF_SENT_5,
+	CXIDV_TELEM_HNI_PAUSE_XOFF_SENT_6,
+	CXIDV_TELEM_HNI_PAUSE_XOFF_SENT_7,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_0,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_1,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_2,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_3,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_4,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_5,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_6,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_7,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_8,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_9,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_10,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_11,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_12,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_13,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_14,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_0,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_1,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_2,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_3,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_4,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_5,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_6,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_7,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_8,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_9,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_10,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_11,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_12,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_13,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_14,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_15,
+	CXIDV_TELEM_HNI_PCS_GOOD_CW,
+	CXIDV_TELEM_HNI_PCS_PML_MBE_ERROR_CNT,
+	CXIDV_TELEM_HNI_PCS_PML_SBE_ERROR_CNT,
+	CXIDV_TELEM_HNI_PCS_UNCORRECTED_CW,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_0,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_1,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_2,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_3,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_4,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_5,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_6,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_7,
+	CXIDV_TELEM_HNI_PKTS_RECV_BY_TC_0,
+	CXIDV_TELEM_HNI_PKTS_RECV_BY_TC_1,
+	CXIDV_TELEM_HNI_PKTS_RECV_BY_TC_2,
+	CXIDV_TELEM_HNI_PKTS_RECV_BY_TC_3,
+	CXIDV_TELEM_HNI_PKTS_RECV_BY_TC_4,
+	CXIDV_TELEM_HNI_PKTS_RECV_BY_TC_5,
+	CXIDV_TELEM_HNI_PKTS_RECV_BY_TC_6,
+	CXIDV_TELEM_HNI_PKTS_RECV_BY_TC_7,
+	CXIDV_TELEM_HNI_PKTS_SENT_BY_TC_0,
+	CXIDV_TELEM_HNI_PKTS_SENT_BY_TC_1,
+	CXIDV_TELEM_HNI_PKTS_SENT_BY_TC_2,
+	CXIDV_TELEM_HNI_PKTS_SENT_BY_TC_3,
+	CXIDV_TELEM_HNI_PKTS_SENT_BY_TC_4,
+	CXIDV_TELEM_HNI_PKTS_SENT_BY_TC_5,
+	CXIDV_TELEM_HNI_PKTS_SENT_BY_TC_6,
+	CXIDV_TELEM_HNI_PKTS_SENT_BY_TC_7,
+	CXIDV_TELEM_HNI_RX_BAD_IEEE,
+	CXIDV_TELEM_HNI_RX_BAD_OPT,
+	CXIDV_TELEM_HNI_RX_FRAGMENT,
+	CXIDV_TELEM_HNI_RX_JABBER,
+	CXIDV_TELEM_HNI_RX_OK_27,
+	CXIDV_TELEM_HNI_RX_OK_35,
+	CXIDV_TELEM_HNI_RX_OK_36_TO_63,
+	CXIDV_TELEM_HNI_RX_OK_64,
+	CXIDV_TELEM_HNI_RX_OK_65_TO_127,
+	CXIDV_TELEM_HNI_RX_OK_128_TO_255,
+	CXIDV_TELEM_HNI_RX_OK_256_TO_511,
+	CXIDV_TELEM_HNI_RX_OK_512_TO_1023,
+	CXIDV_TELEM_HNI_RX_OK_1024_TO_2047,
+	CXIDV_TELEM_HNI_RX_OK_2048_TO_4095,
+	CXIDV_TELEM_HNI_RX_OK_4096_TO_8191,
+	CXIDV_TELEM_HNI_RX_OK_8192_TO_MAX,
+	CXIDV_TELEM_HNI_RX_OK_BAD_OP_CODE,
+	CXIDV_TELEM_HNI_RX_OK_BROADCAST,
+	CXIDV_TELEM_HNI_RX_OK_FLOW_CONTROL,
+	CXIDV_TELEM_HNI_RX_OK_IEEE,
+	CXIDV_TELEM_HNI_RX_OK_LEN_TYPE_ERROR,
+	CXIDV_TELEM_HNI_RX_OK_MAC_CONTROL,
+	CXIDV_TELEM_HNI_RX_OK_MULTICAST,
+	CXIDV_TELEM_HNI_RX_OK_OPT,
+	CXIDV_TELEM_HNI_RX_OK_TAGGED,
+	CXIDV_TELEM_HNI_RX_OK_TOO_LONG,
+	CXIDV_TELEM_HNI_RX_OK_UNDERSIZE,
+	CXIDV_TELEM_HNI_RX_PAUSED_0,
+	CXIDV_TELEM_HNI_RX_PAUSED_1,
+	CXIDV_TELEM_HNI_RX_PAUSED_2,
+	CXIDV_TELEM_HNI_RX_PAUSED_3,
+	CXIDV_TELEM_HNI_RX_PAUSED_4,
+	CXIDV_TELEM_HNI_RX_PAUSED_5,
+	CXIDV_TELEM_HNI_RX_PAUSED_6,
+	CXIDV_TELEM_HNI_RX_PAUSED_7,
+	CXIDV_TELEM_HNI_RX_PAUSED_STD,
+	CXIDV_TELEM_HNI_RX_STALL_IXE_FIFO,
+	CXIDV_TELEM_HNI_RX_STALL_IXE_PKTBUF_0,
+	CXIDV_TELEM_HNI_RX_STALL_IXE_PKTBUF_1,
+	CXIDV_TELEM_HNI_RX_STALL_IXE_PKTBUF_2,
+	CXIDV_TELEM_HNI_RX_STALL_IXE_PKTBUF_3,
+	CXIDV_TELEM_HNI_RX_STALL_IXE_PKTBUF_4,
+	CXIDV_TELEM_HNI_RX_STALL_IXE_PKTBUF_5,
+	CXIDV_TELEM_HNI_RX_STALL_IXE_PKTBUF_6,
+	CXIDV_TELEM_HNI_RX_STALL_IXE_PKTBUF_7,
+	CXIDV_TELEM_HNI_STS_RX_BAD_OCTETS,
+	CXIDV_TELEM_HNI_STS_RX_OCTETS_BCAST,
+	CXIDV_TELEM_HNI_STS_RX_OCTETS_IEEE,
+	CXIDV_TELEM_HNI_STS_RX_OCTETS_MULTI,
+	CXIDV_TELEM_HNI_STS_RX_OCTETS_OPT,
+	CXIDV_TELEM_HNI_STS_RX_OK_OCTETS,
+	CXIDV_TELEM_HNI_STS_TX_BAD_OCTETS,
+	CXIDV_TELEM_HNI_STS_TX_OCTETS_BCAST,
+	CXIDV_TELEM_HNI_STS_TX_OCTETS_IEEE,
+	CXIDV_TELEM_HNI_STS_TX_OCTETS_MULTI,
+	CXIDV_TELEM_HNI_STS_TX_OCTETS_OPT,
+	CXIDV_TELEM_HNI_STS_TX_OK_OCTETS,
+	CXIDV_TELEM_HNI_TX_OK_27,
+	CXIDV_TELEM_HNI_TX_OK_35,
+	CXIDV_TELEM_HNI_TX_OK_36_TO_63,
+	CXIDV_TELEM_HNI_TX_OK_64,
+	CXIDV_TELEM_HNI_TX_OK_65_TO_127,
+	CXIDV_TELEM_HNI_TX_OK_128_TO_255,
+	CXIDV_TELEM_HNI_TX_OK_256_TO_511,
+	CXIDV_TELEM_HNI_TX_OK_512_TO_1023,
+	CXIDV_TELEM_HNI_TX_OK_1024_TO_2047,
+	CXIDV_TELEM_HNI_TX_OK_2048_TO_4095,
+	CXIDV_TELEM_HNI_TX_OK_4096_TO_8191,
+	CXIDV_TELEM_HNI_TX_OK_8192_TO_MAX,
+	CXIDV_TELEM_HNI_TX_OK_BROADCAST,
+	CXIDV_TELEM_HNI_TX_OK_IEEE,
+	CXIDV_TELEM_HNI_TX_OK_MULTICAST,
+	CXIDV_TELEM_HNI_TX_OK_OPT,
+	CXIDV_TELEM_HNI_TX_OK_TAGGED,
+	CXIDV_TELEM_HNI_TX_OPT_PADDED,
+	CXIDV_TELEM_HNI_TX_OPT_SIZE_ERR,
+	CXIDV_TELEM_HNI_TX_PAUSED_0,
+	CXIDV_TELEM_HNI_TX_PAUSED_1,
+	CXIDV_TELEM_HNI_TX_PAUSED_2,
+	CXIDV_TELEM_HNI_TX_PAUSED_3,
+	CXIDV_TELEM_HNI_TX_PAUSED_4,
+	CXIDV_TELEM_HNI_TX_PAUSED_5,
+	CXIDV_TELEM_HNI_TX_PAUSED_6,
+	CXIDV_TELEM_HNI_TX_PAUSED_7,
+	CXIDV_TELEM_HNI_TX_POISONED_IEEE,
+	CXIDV_TELEM_HNI_TX_POISONED_OPT,
+	CXIDV_TELEM_HNI_TX_STALL_LLR,
+	CXIDV_TELEM_HNI_TX_STD_PADDED,
+	CXIDV_TELEM_HNI_TX_STD_SIZE_ERR,
+	CXIDV_TELEM_HNI_UCOR_ECC_ERR_CNTR,
+};
+
+static const uint64_t set_ixe[] = {
+	CXIDV_TELEM_IXE_DISP_AMO_CONFLICTS,
+	CXIDV_TELEM_IXE_DISP_AMO_EVENTS,
+	CXIDV_TELEM_IXE_DISP_ATU_FLUSH_REQS,
+	CXIDV_TELEM_IXE_DISP_ATU_REQS,
+	CXIDV_TELEM_IXE_DISP_ATU_RESPS,
+	CXIDV_TELEM_IXE_DISP_ATU_RESPS_OK,
+	CXIDV_TELEM_IXE_DISP_DMAWR_REQS,
+	CXIDV_TELEM_IXE_DISP_DMAWR_RESPS,
+	CXIDV_TELEM_IXE_DISP_DMAWR_RESPS_OK,
+	CXIDV_TELEM_IXE_DISP_ETH_EVENTS,
+	CXIDV_TELEM_IXE_DISP_LPE_AMOS,
+	CXIDV_TELEM_IXE_DISP_LPE_AMOS_OK,
+	CXIDV_TELEM_IXE_DISP_LPE_GETS,
+	CXIDV_TELEM_IXE_DISP_LPE_GETS_OK,
+	CXIDV_TELEM_IXE_DISP_LPE_PUTS,
+	CXIDV_TELEM_IXE_DISP_LPE_PUTS_OK,
+	CXIDV_TELEM_IXE_DISP_MST_GETS,
+	CXIDV_TELEM_IXE_DISP_MST_GETS_OK,
+	CXIDV_TELEM_IXE_DISP_MST_PUTS,
+	CXIDV_TELEM_IXE_DISP_MST_PUTS_OK,
+	CXIDV_TELEM_IXE_DISP_OXE_RESPS,
+	CXIDV_TELEM_IXE_DISP_PCT_GETCOMP,
+	CXIDV_TELEM_IXE_DISP_PUT_EVENTS,
+	CXIDV_TELEM_IXE_DISP_RPU_ERR_REQS,
+	CXIDV_TELEM_IXE_DISP_RPU_RESPS,
+	CXIDV_TELEM_IXE_DISP_STALL_ATU_CDT,
+	CXIDV_TELEM_IXE_DISP_STALL_ATU_FIFO,
+	CXIDV_TELEM_IXE_DISP_STALL_CONFLICT,
+	CXIDV_TELEM_IXE_DISP_STALL_ERR_FIFO,
+	CXIDV_TELEM_IXE_DISP_STALL_GCOMP_FIFO,
+	CXIDV_TELEM_IXE_DISP_STALL_GRR_ID,
+	CXIDV_TELEM_IXE_DISP_STALL_MDID_CDTS,
+	CXIDV_TELEM_IXE_DISP_STALL_MST_MATCH_FIFO,
+	CXIDV_TELEM_IXE_DISP_STALL_PUT_RESP,
+	CXIDV_TELEM_IXE_DISP_STALL_RESP_FIFO,
+	CXIDV_TELEM_IXE_DISP_WR_CONFLICTS,
+	CXIDV_TELEM_IXE_DMAWR_AMO_EX_INEXACT,
+	CXIDV_TELEM_IXE_DMAWR_AMO_EX_INVALID,
+	CXIDV_TELEM_IXE_DMAWR_AMO_EX_OVERFLOW,
+	CXIDV_TELEM_IXE_DMAWR_AMO_EX_UNDERFLOW,
+	CXIDV_TELEM_IXE_DMAWR_AMO_INVALID_OP,
+	CXIDV_TELEM_IXE_DMAWR_AMO_LEN_ERR,
+	CXIDV_TELEM_IXE_DMAWR_AMO_MISALIGNED,
+	CXIDV_TELEM_IXE_DMAWR_CPU_AMO_REQS,
+	CXIDV_TELEM_IXE_DMAWR_CPU_FTCH_AMO_REQS,
+	CXIDV_TELEM_IXE_DMAWR_FLUSH_REQS,
+	CXIDV_TELEM_IXE_DMAWR_NIC_AMO_REQS,
+	CXIDV_TELEM_IXE_DMAWR_P_PASS_NP_CNT,
+	CXIDV_TELEM_IXE_DMAWR_PCIE_ERR_POISONED,
+	CXIDV_TELEM_IXE_DMAWR_PCIE_UNSUCCESS_CMPL,
+	CXIDV_TELEM_IXE_DMAWR_REQ_NO_WRITE_REQS,
+	CXIDV_TELEM_IXE_DMAWR_STALL_FTCH_AMO_CNT,
+	CXIDV_TELEM_IXE_DMAWR_STALL_NP_CDT,
+	CXIDV_TELEM_IXE_DMAWR_STALL_NP_REQ_CNT,
+	CXIDV_TELEM_IXE_DMAWR_STALL_P_CDT,
+	CXIDV_TELEM_IXE_DMAWR_WRITE_REQS,
+	CXIDV_TELEM_IXE_GET_LEN_ERRORS,
+	CXIDV_TELEM_IXE_HDR_CHECKSUM_ERRORS,
+	CXIDV_TELEM_IXE_HDR_ECC_ERRORS,
+	CXIDV_TELEM_IXE_HRP_REQ_ERRORS,
+	CXIDV_TELEM_IXE_IP_OPTIONS_ERRORS,
+	CXIDV_TELEM_IXE_IPV4_CHECKSUM_ERRORS,
+	CXIDV_TELEM_IXE_MEM_COR_ERR_CNTR,
+	CXIDV_TELEM_IXE_MEM_UCOR_ERR_CNTR,
+	CXIDV_TELEM_IXE_PARSER_PAR_ERRORS,
+	CXIDV_TELEM_IXE_PBUF_RD_ERRORS,
+	CXIDV_TELEM_IXE_POOL_ECN_PKTS_0,
+	CXIDV_TELEM_IXE_POOL_ECN_PKTS_1,
+	CXIDV_TELEM_IXE_POOL_ECN_PKTS_2,
+	CXIDV_TELEM_IXE_POOL_ECN_PKTS_3,
+	CXIDV_TELEM_IXE_POOL_NO_ECN_PKTS_0,
+	CXIDV_TELEM_IXE_POOL_NO_ECN_PKTS_1,
+	CXIDV_TELEM_IXE_POOL_NO_ECN_PKTS_2,
+	CXIDV_TELEM_IXE_POOL_NO_ECN_PKTS_3,
+	CXIDV_TELEM_IXE_PORT_DFA_MISMATCH,
+	CXIDV_TELEM_IXE_ROCE_ICRC_ERROR,
+	CXIDV_TELEM_IXE_RX_ETH_SEG,
+	CXIDV_TELEM_IXE_RX_IPV4_PKT,
+	CXIDV_TELEM_IXE_RX_IPV6_PKT,
+	CXIDV_TELEM_IXE_RX_PKT_DROP_IXE_PARSER,
+	CXIDV_TELEM_IXE_RX_PKT_DROP_PCT,
+	CXIDV_TELEM_IXE_RX_PKT_DROP_RMU_NORSP,
+	CXIDV_TELEM_IXE_RX_PKT_DROP_RMU_WRSP,
+	CXIDV_TELEM_IXE_RX_PKT_IPV4_OPTIONS,
+	CXIDV_TELEM_IXE_RX_PKT_IPV6_OPTIONS,
+	CXIDV_TELEM_IXE_RX_PTL_CONNMGMT_PKT,
+	CXIDV_TELEM_IXE_RX_PTL_CONTINUATION_PKT,
+	CXIDV_TELEM_IXE_RX_PTL_GEN_PKT,
+	CXIDV_TELEM_IXE_RX_PTL_MR_MSGS,
+	CXIDV_TELEM_IXE_RX_PTL_MSGS,
+	CXIDV_TELEM_IXE_RX_PTL_MULTI_MSGS,
+	CXIDV_TELEM_IXE_RX_PTL_RESPONSE_PKT,
+	CXIDV_TELEM_IXE_RX_PTL_RESTRICTED_PKT,
+	CXIDV_TELEM_IXE_RX_PTL_SMALLMSG_PKT,
+	CXIDV_TELEM_IXE_RX_PTL_SML_AMO_PKT,
+	CXIDV_TELEM_IXE_RX_PTL_SML_PKT,
+	CXIDV_TELEM_IXE_RX_PTL_UNRESTRICTED_PKT,
+	CXIDV_TELEM_IXE_RX_ROCE_PKT,
+	CXIDV_TELEM_IXE_RX_ROCE_SEG,
+	CXIDV_TELEM_IXE_RX_ROCE_SPSEG,
+	CXIDV_TELEM_IXE_RX_TCP_PKT,
+	CXIDV_TELEM_IXE_RX_UDP_PKT,
+	CXIDV_TELEM_IXE_RX_UNRECOGNIZED_PKT,
+	CXIDV_TELEM_IXE_TC_REQ_ECN_PKTS_0,
+	CXIDV_TELEM_IXE_TC_REQ_ECN_PKTS_1,
+	CXIDV_TELEM_IXE_TC_REQ_ECN_PKTS_2,
+	CXIDV_TELEM_IXE_TC_REQ_ECN_PKTS_3,
+	CXIDV_TELEM_IXE_TC_REQ_ECN_PKTS_4,
+	CXIDV_TELEM_IXE_TC_REQ_ECN_PKTS_5,
+	CXIDV_TELEM_IXE_TC_REQ_ECN_PKTS_6,
+	CXIDV_TELEM_IXE_TC_REQ_ECN_PKTS_7,
+	CXIDV_TELEM_IXE_TC_REQ_NO_ECN_PKTS_0,
+	CXIDV_TELEM_IXE_TC_REQ_NO_ECN_PKTS_1,
+	CXIDV_TELEM_IXE_TC_REQ_NO_ECN_PKTS_2,
+	CXIDV_TELEM_IXE_TC_REQ_NO_ECN_PKTS_3,
+	CXIDV_TELEM_IXE_TC_REQ_NO_ECN_PKTS_4,
+	CXIDV_TELEM_IXE_TC_REQ_NO_ECN_PKTS_5,
+	CXIDV_TELEM_IXE_TC_REQ_NO_ECN_PKTS_6,
+	CXIDV_TELEM_IXE_TC_REQ_NO_ECN_PKTS_7,
+	CXIDV_TELEM_IXE_TC_RSP_ECN_PKTS_0,
+	CXIDV_TELEM_IXE_TC_RSP_ECN_PKTS_1,
+	CXIDV_TELEM_IXE_TC_RSP_ECN_PKTS_2,
+	CXIDV_TELEM_IXE_TC_RSP_ECN_PKTS_3,
+	CXIDV_TELEM_IXE_TC_RSP_ECN_PKTS_4,
+	CXIDV_TELEM_IXE_TC_RSP_ECN_PKTS_5,
+	CXIDV_TELEM_IXE_TC_RSP_ECN_PKTS_6,
+	CXIDV_TELEM_IXE_TC_RSP_ECN_PKTS_7,
+	CXIDV_TELEM_IXE_TC_RSP_NO_ECN_PKTS_0,
+	CXIDV_TELEM_IXE_TC_RSP_NO_ECN_PKTS_1,
+	CXIDV_TELEM_IXE_TC_RSP_NO_ECN_PKTS_2,
+	CXIDV_TELEM_IXE_TC_RSP_NO_ECN_PKTS_3,
+	CXIDV_TELEM_IXE_TC_RSP_NO_ECN_PKTS_4,
+	CXIDV_TELEM_IXE_TC_RSP_NO_ECN_PKTS_5,
+	CXIDV_TELEM_IXE_TC_RSP_NO_ECN_PKTS_6,
+	CXIDV_TELEM_IXE_TC_RSP_NO_ECN_PKTS_7,
+};
+
+static const uint64_t set_lpe[] = {
+	CXIDV_TELEM_LPE_AMO_CMDS,
+	CXIDV_TELEM_LPE_APPEND_CMDS_0,
+	CXIDV_TELEM_LPE_APPEND_CMDS_1,
+	CXIDV_TELEM_LPE_APPEND_CMDS_2,
+	CXIDV_TELEM_LPE_APPEND_CMDS_3,
+	CXIDV_TELEM_LPE_APPEND_SUCCESS_0,
+	CXIDV_TELEM_LPE_APPEND_SUCCESS_1,
+	CXIDV_TELEM_LPE_APPEND_SUCCESS_2,
+	CXIDV_TELEM_LPE_APPEND_SUCCESS_3,
+	CXIDV_TELEM_LPE_CFG_EVENT_CNTS_OVF_CNT,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_SHARED_0,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_SHARED_1,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_SHARED_2,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_SHARED_3,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_SHARED_ALLOCATED_0,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_SHARED_ALLOCATED_1,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_SHARED_ALLOCATED_2,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_SHARED_ALLOCATED_3,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_TOTAL_0,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_TOTAL_1,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_TOTAL_2,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_TOTAL_3,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_TOTAL_ALLOCATED_0,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_TOTAL_ALLOCATED_1,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_TOTAL_ALLOCATED_2,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_TOTAL_ALLOCATED_3,
+	CXIDV_TELEM_LPE_CYC_BLOCKED_IXE_GET,
+	CXIDV_TELEM_LPE_CYC_BLOCKED_IXE_PUT,
+	CXIDV_TELEM_LPE_CYC_BLOCKED_LOSSLESS,
+	CXIDV_TELEM_LPE_CYC_NO_RDY_CDTS,
+	CXIDV_TELEM_LPE_CYC_RRQ_BLOCKED_0,
+	CXIDV_TELEM_LPE_CYC_RRQ_BLOCKED_1,
+	CXIDV_TELEM_LPE_CYC_RRQ_BLOCKED_2,
+	CXIDV_TELEM_LPE_CYC_RRQ_BLOCKED_3,
+	CXIDV_TELEM_LPE_ERR_ENTRY_NOT_FOUND_CANT_ALLOC_UNEXPECTED,
+	CXIDV_TELEM_LPE_ERR_ENTRY_NOT_FOUND_EQ_FULL,
+	CXIDV_TELEM_LPE_ERR_ENTRY_NOT_FOUND_ETHERNET,
+	CXIDV_TELEM_LPE_ERR_ENTRY_NOT_FOUND_NO_MATCH_IN_OVERFLOW,
+	CXIDV_TELEM_LPE_ERR_ENTRY_NOT_FOUND_REQ_EMPTY,
+	CXIDV_TELEM_LPE_ERR_ENTRY_NOT_FOUND_UNLINK_FAILED,
+	CXIDV_TELEM_LPE_ERR_EQ_DISABLED,
+	CXIDV_TELEM_LPE_ERR_ILLEGAL_OP,
+	CXIDV_TELEM_LPE_ERR_INVALID_ENDPOINT,
+	CXIDV_TELEM_LPE_ERR_NO_SPACE_APPEND,
+	CXIDV_TELEM_LPE_ERR_NO_SPACE_NET,
+	CXIDV_TELEM_LPE_ERR_OP_VIOLATION,
+	CXIDV_TELEM_LPE_ERR_PT_DISABLED_CANT_ALLOC_UNEXPECTED,
+	CXIDV_TELEM_LPE_ERR_PT_DISABLED_EQ_FULL,
+	CXIDV_TELEM_LPE_ERR_PT_DISABLED_NO_MATCH_IN_OVERFLOW,
+	CXIDV_TELEM_LPE_ERR_PT_DISABLED_REQ_EMPTY,
+	CXIDV_TELEM_LPE_ERR_PTLTE_SW_MANAGED,
+	CXIDV_TELEM_LPE_ERR_RESTRICTED_UNICAST,
+	CXIDV_TELEM_LPE_ERR_SEARCH_NO_MATCH,
+	CXIDV_TELEM_LPE_ERR_SETSTATE_NO_MATCH,
+	CXIDV_TELEM_LPE_ERR_SRC_ERROR,
+	CXIDV_TELEM_LPE_EVENT_ATOMIC_OVERFLOW,
+	CXIDV_TELEM_LPE_EVENT_FETCH_ATOMIC_OVERFLOW,
+	CXIDV_TELEM_LPE_EVENT_GET_OVERFLOW,
+	CXIDV_TELEM_LPE_EVENT_LINK,
+	CXIDV_TELEM_LPE_EVENT_PUT_OVERFLOW,
+	CXIDV_TELEM_LPE_EVENT_RENDEZVOUS,
+	CXIDV_TELEM_LPE_EVENT_SEARCH,
+	CXIDV_TELEM_LPE_EVENT_STATECHANGE,
+	CXIDV_TELEM_LPE_EVENT_UNLINK,
+	CXIDV_TELEM_LPE_FAIL_CNTR,
+	CXIDV_TELEM_LPE_FAMO_CMDS,
+	CXIDV_TELEM_LPE_GET_CMDS,
+	CXIDV_TELEM_LPE_MEM_COR_ERR_CNTR,
+	CXIDV_TELEM_LPE_MEM_UCOR_ERR_CNTR,
+	CXIDV_TELEM_LPE_NET_MATCH_LOCAL_0,
+	CXIDV_TELEM_LPE_NET_MATCH_LOCAL_1,
+	CXIDV_TELEM_LPE_NET_MATCH_LOCAL_2,
+	CXIDV_TELEM_LPE_NET_MATCH_LOCAL_3,
+	CXIDV_TELEM_LPE_NET_MATCH_OVERFLOW_0,
+	CXIDV_TELEM_LPE_NET_MATCH_OVERFLOW_1,
+	CXIDV_TELEM_LPE_NET_MATCH_OVERFLOW_2,
+	CXIDV_TELEM_LPE_NET_MATCH_OVERFLOW_3,
+	CXIDV_TELEM_LPE_NET_MATCH_PRIORITY_0,
+	CXIDV_TELEM_LPE_NET_MATCH_PRIORITY_1,
+	CXIDV_TELEM_LPE_NET_MATCH_PRIORITY_2,
+	CXIDV_TELEM_LPE_NET_MATCH_PRIORITY_3,
+	CXIDV_TELEM_LPE_NET_MATCH_REQUEST_0,
+	CXIDV_TELEM_LPE_NET_MATCH_REQUEST_1,
+	CXIDV_TELEM_LPE_NET_MATCH_REQUEST_2,
+	CXIDV_TELEM_LPE_NET_MATCH_REQUEST_3,
+	CXIDV_TELEM_LPE_NET_MATCH_REQUESTS_0,
+	CXIDV_TELEM_LPE_NET_MATCH_REQUESTS_1,
+	CXIDV_TELEM_LPE_NET_MATCH_REQUESTS_2,
+	CXIDV_TELEM_LPE_NET_MATCH_REQUESTS_3,
+	CXIDV_TELEM_LPE_NET_MATCH_SUCCESS_0,
+	CXIDV_TELEM_LPE_NET_MATCH_SUCCESS_1,
+	CXIDV_TELEM_LPE_NET_MATCH_SUCCESS_2,
+	CXIDV_TELEM_LPE_NET_MATCH_SUCCESS_3,
+	CXIDV_TELEM_LPE_NET_MATCH_USEONCE_0,
+	CXIDV_TELEM_LPE_NET_MATCH_USEONCE_1,
+	CXIDV_TELEM_LPE_NET_MATCH_USEONCE_2,
+	CXIDV_TELEM_LPE_NET_MATCH_USEONCE_3,
+	CXIDV_TELEM_LPE_NUM_TRUNCATED_0,
+	CXIDV_TELEM_LPE_NUM_TRUNCATED_1,
+	CXIDV_TELEM_LPE_NUM_TRUNCATED_2,
+	CXIDV_TELEM_LPE_NUM_TRUNCATED_3,
+	CXIDV_TELEM_LPE_PLEC_ALLOCS,
+	CXIDV_TELEM_LPE_PLEC_FREES,
+	CXIDV_TELEM_LPE_PLEC_FREES_CSR,
+	CXIDV_TELEM_LPE_PLEC_HITS,
+	CXIDV_TELEM_LPE_PUT_CMDS,
+	CXIDV_TELEM_LPE_RENDEZVOUS_PUT_CMDS,
+	CXIDV_TELEM_LPE_RNDZV_PUTS_0,
+	CXIDV_TELEM_LPE_RNDZV_PUTS_1,
+	CXIDV_TELEM_LPE_RNDZV_PUTS_2,
+	CXIDV_TELEM_LPE_RNDZV_PUTS_3,
+	CXIDV_TELEM_LPE_RNDZV_PUTS_OFFLOADED_0,
+	CXIDV_TELEM_LPE_RNDZV_PUTS_OFFLOADED_1,
+	CXIDV_TELEM_LPE_RNDZV_PUTS_OFFLOADED_2,
+	CXIDV_TELEM_LPE_RNDZV_PUTS_OFFLOADED_3,
+	CXIDV_TELEM_LPE_SEARCH_CMDS,
+	CXIDV_TELEM_LPE_SEARCH_DELETE_CMDS,
+	CXIDV_TELEM_LPE_SEARCH_DELETE_FAIL,
+	CXIDV_TELEM_LPE_SEARCH_DELETE_SUCCESS,
+	CXIDV_TELEM_LPE_SEARCH_FAIL,
+	CXIDV_TELEM_LPE_SEARCH_NID_ANY_0,
+	CXIDV_TELEM_LPE_SEARCH_NID_ANY_1,
+	CXIDV_TELEM_LPE_SEARCH_NID_ANY_2,
+	CXIDV_TELEM_LPE_SEARCH_NID_ANY_3,
+	CXIDV_TELEM_LPE_SEARCH_PID_ANY_0,
+	CXIDV_TELEM_LPE_SEARCH_PID_ANY_1,
+	CXIDV_TELEM_LPE_SEARCH_PID_ANY_2,
+	CXIDV_TELEM_LPE_SEARCH_PID_ANY_3,
+	CXIDV_TELEM_LPE_SEARCH_RANK_ANY_0,
+	CXIDV_TELEM_LPE_SEARCH_RANK_ANY_1,
+	CXIDV_TELEM_LPE_SEARCH_RANK_ANY_2,
+	CXIDV_TELEM_LPE_SEARCH_RANK_ANY_3,
+	CXIDV_TELEM_LPE_SEARCH_SUCCESS,
+	CXIDV_TELEM_LPE_SETSTATE_CMDS_0,
+	CXIDV_TELEM_LPE_SETSTATE_CMDS_1,
+	CXIDV_TELEM_LPE_SETSTATE_CMDS_2,
+	CXIDV_TELEM_LPE_SETSTATE_CMDS_3,
+	CXIDV_TELEM_LPE_SETSTATE_SUCCESS_0,
+	CXIDV_TELEM_LPE_SETSTATE_SUCCESS_1,
+	CXIDV_TELEM_LPE_SETSTATE_SUCCESS_2,
+	CXIDV_TELEM_LPE_SETSTATE_SUCCESS_3,
+	CXIDV_TELEM_LPE_STS_APP_MATCH_ATTEMPTS_0,
+	CXIDV_TELEM_LPE_STS_APP_MATCH_ATTEMPTS_1,
+	CXIDV_TELEM_LPE_STS_APP_MATCH_ATTEMPTS_2,
+	CXIDV_TELEM_LPE_STS_APP_MATCH_ATTEMPTS_3,
+	CXIDV_TELEM_LPE_STS_APP_MAX_ATTEMPTS_MAX_0,
+	CXIDV_TELEM_LPE_STS_APP_MAX_ATTEMPTS_MAX_1,
+	CXIDV_TELEM_LPE_STS_APP_MAX_ATTEMPTS_MAX_2,
+	CXIDV_TELEM_LPE_STS_APP_MAX_ATTEMPTS_MAX_3,
+	CXIDV_TELEM_LPE_STS_APP_MAX_ATTEMPTS_NUM_PBUF_ENTRIES_0,
+	CXIDV_TELEM_LPE_STS_APP_MAX_ATTEMPTS_NUM_PBUF_ENTRIES_1,
+	CXIDV_TELEM_LPE_STS_APP_MAX_ATTEMPTS_NUM_PBUF_ENTRIES_2,
+	CXIDV_TELEM_LPE_STS_APP_MAX_ATTEMPTS_NUM_PBUF_ENTRIES_3,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_LOAD_0,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_LOAD_1,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_LOAD_2,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_LOAD_3,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_MAX_0,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_MAX_1,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_MAX_2,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_MAX_3,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_PTLTE_LOAD_0,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_PTLTE_LOAD_1,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_PTLTE_LOAD_2,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_PTLTE_LOAD_3,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_PTLTE_MAX_0,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_PTLTE_MAX_1,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_PTLTE_MAX_2,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_PTLTE_MAX_3,
+	CXIDV_TELEM_LPE_STS_NET_MATCH_ATTEMPTS_0,
+	CXIDV_TELEM_LPE_STS_NET_MATCH_ATTEMPTS_1,
+	CXIDV_TELEM_LPE_STS_NET_MATCH_ATTEMPTS_2,
+	CXIDV_TELEM_LPE_STS_NET_MATCH_ATTEMPTS_3,
+	CXIDV_TELEM_LPE_STS_NET_MAX_ATTEMPTS_MAX_0,
+	CXIDV_TELEM_LPE_STS_NET_MAX_ATTEMPTS_MAX_1,
+	CXIDV_TELEM_LPE_STS_NET_MAX_ATTEMPTS_MAX_2,
+	CXIDV_TELEM_LPE_STS_NET_MAX_ATTEMPTS_MAX_3,
+	CXIDV_TELEM_LPE_STS_NET_MAX_ATTEMPTS_NUM_PBUF_ENTRIES_0,
+	CXIDV_TELEM_LPE_STS_NET_MAX_ATTEMPTS_NUM_PBUF_ENTRIES_1,
+	CXIDV_TELEM_LPE_STS_NET_MAX_ATTEMPTS_NUM_PBUF_ENTRIES_2,
+	CXIDV_TELEM_LPE_STS_NET_MAX_ATTEMPTS_NUM_PBUF_ENTRIES_3,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_0,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_1,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_2,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_3,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_4,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_5,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_6,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_7,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_8,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_9,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_10,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_11,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_12,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_13,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_14,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_15,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_16,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_17,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_18,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_19,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_20,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_21,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_22,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_23,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_24,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_25,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_26,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_27,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_28,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_29,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_30,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_31,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_32,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_33,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_34,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_35,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_36,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_37,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_38,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_39,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_40,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_41,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_42,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_43,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_44,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_45,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_46,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_47,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_48,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_49,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_50,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_51,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_52,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_53,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_54,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_55,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_56,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_57,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_58,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_59,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_60,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_61,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_62,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_63,
+	CXIDV_TELEM_LPE_SUCCESS_CNTR,
+	CXIDV_TELEM_LPE_UNEXPECTED_GET_AMO_0,
+	CXIDV_TELEM_LPE_UNEXPECTED_GET_AMO_1,
+	CXIDV_TELEM_LPE_UNEXPECTED_GET_AMO_2,
+	CXIDV_TELEM_LPE_UNEXPECTED_GET_AMO_3,
+	CXIDV_TELEM_LPE_UNLINK_CMDS,
+	CXIDV_TELEM_LPE_UNLINK_SUCCESS,
+};
+
+static const uint64_t set_mb[] = {
+	CXIDV_TELEM_MB_CFG_EVENT_CNTS_OVF_CNT,	  CXIDV_TELEM_MB_CMC_AXI_RD_REQUESTS_0,
+	CXIDV_TELEM_MB_CMC_AXI_RD_REQUESTS_1,	  CXIDV_TELEM_MB_CMC_AXI_RD_REQUESTS_2,
+	CXIDV_TELEM_MB_CMC_AXI_RD_REQUESTS_3,	  CXIDV_TELEM_MB_CMC_AXI_WR_REQUESTS_0,
+	CXIDV_TELEM_MB_CMC_AXI_WR_REQUESTS_1,	  CXIDV_TELEM_MB_CMC_AXI_WR_REQUESTS_2,
+	CXIDV_TELEM_MB_CMC_AXI_WR_REQUESTS_3,	  CXIDV_TELEM_MB_CQ_LSA0_TRIGGER_EVENTS_0,
+	CXIDV_TELEM_MB_CQ_LSA0_TRIGGER_EVENTS_1,  CXIDV_TELEM_MB_CQ_LSA1_TRIGGER_EVENTS_0,
+	CXIDV_TELEM_MB_CQ_LSA1_TRIGGER_EVENTS_1,  CXIDV_TELEM_MB_CRMC_AXI_RD_REQUESTS_0,
+	CXIDV_TELEM_MB_CRMC_AXI_RD_REQUESTS_1,	  CXIDV_TELEM_MB_CRMC_AXI_RD_REQUESTS_2,
+	CXIDV_TELEM_MB_CRMC_AXI_WR_REQUESTS_0,	  CXIDV_TELEM_MB_CRMC_AXI_WR_REQUESTS_1,
+	CXIDV_TELEM_MB_CRMC_AXI_WR_REQUESTS_2,	  CXIDV_TELEM_MB_CRMC_RD_ERROR_0,
+	CXIDV_TELEM_MB_CRMC_RD_ERROR_1,		  CXIDV_TELEM_MB_CRMC_RD_ERROR_2,
+	CXIDV_TELEM_MB_CRMC_RING_MBE_0,		  CXIDV_TELEM_MB_CRMC_RING_MBE_1,
+	CXIDV_TELEM_MB_CRMC_RING_MBE_2,		  CXIDV_TELEM_MB_CRMC_RING_RD_REQUESTS_0,
+	CXIDV_TELEM_MB_CRMC_RING_RD_REQUESTS_1,	  CXIDV_TELEM_MB_CRMC_RING_RD_REQUESTS_2,
+	CXIDV_TELEM_MB_CRMC_RING_SBE_0,		  CXIDV_TELEM_MB_CRMC_RING_SBE_1,
+	CXIDV_TELEM_MB_CRMC_RING_SBE_2,		  CXIDV_TELEM_MB_CRMC_RING_WR_REQUESTS_0,
+	CXIDV_TELEM_MB_CRMC_RING_WR_REQUESTS_1,	  CXIDV_TELEM_MB_CRMC_RING_WR_REQUESTS_2,
+	CXIDV_TELEM_MB_CRMC_WR_ERROR_0,		  CXIDV_TELEM_MB_CRMC_WR_ERROR_1,
+	CXIDV_TELEM_MB_CRMC_WR_ERROR_2,		  CXIDV_TELEM_MB_EE_LSA0_TRIGGER_EVENTS_0,
+	CXIDV_TELEM_MB_EE_LSA0_TRIGGER_EVENTS_1,  CXIDV_TELEM_MB_EE_LSA1_TRIGGER_EVENTS_0,
+	CXIDV_TELEM_MB_EE_LSA1_TRIGGER_EVENTS_1,  CXIDV_TELEM_MB_IXE_LSA0_TRIGGER_EVENTS_0,
+	CXIDV_TELEM_MB_IXE_LSA0_TRIGGER_EVENTS_1, CXIDV_TELEM_MB_IXE_LSA1_TRIGGER_EVENTS_0,
+	CXIDV_TELEM_MB_IXE_LSA1_TRIGGER_EVENTS_1, CXIDV_TELEM_MB_JAI_AXI_RD_REQUESTS,
+	CXIDV_TELEM_MB_JAI_AXI_WR_REQUESTS,	  CXIDV_TELEM_MB_MB_LSA0_TRIGGER_EVENTS_0,
+	CXIDV_TELEM_MB_MB_LSA0_TRIGGER_EVENTS_1,  CXIDV_TELEM_MB_MB_LSA1_TRIGGER_EVENTS_0,
+	CXIDV_TELEM_MB_MB_LSA1_TRIGGER_EVENTS_1,
+};
+
+static const uint64_t set_mst[] = {
+	CXIDV_TELEM_MST_ALLOCATIONS,
+	CXIDV_TELEM_MST_ERR_CANCELLED,
+	CXIDV_TELEM_MST_MEM_COR_ERR_CNTR,
+	CXIDV_TELEM_MST_MEM_UCOR_ERR_CNTR,
+	CXIDV_TELEM_MST_REQUESTS,
+	CXIDV_TELEM_MST_STALLED_WAITING_EE_CRDTS,
+	CXIDV_TELEM_MST_STALLED_WAITING_FOR_LPE,
+	CXIDV_TELEM_MST_STALLED_WAITING_GET_CRDTS,
+	CXIDV_TELEM_MST_STALLED_WAITING_PUT_CRDTS,
+	CXIDV_TELEM_MST_STS_NUM_REQ,
+};
+
+static const uint64_t set_oxe[] = {
+	CXIDV_TELEM_OXE_CHANNEL_IDLE,
+	CXIDV_TELEM_OXE_ERR_INVALID_AC,
+	CXIDV_TELEM_OXE_ERR_NO_TRANSLATION,
+	CXIDV_TELEM_OXE_ERR_PAGE_PERM,
+	CXIDV_TELEM_OXE_ERR_PAGE_REQ,
+	CXIDV_TELEM_OXE_ERR_PCI_CMPL,
+	CXIDV_TELEM_OXE_ERR_PCI_EP,
+	CXIDV_TELEM_OXE_ERR_TA_ERROR,
+	CXIDV_TELEM_OXE_IGNORE_ERRS,
+	CXIDV_TELEM_OXE_IOI_DMA,
+	CXIDV_TELEM_OXE_IOI_PKTS_ORDERED,
+	CXIDV_TELEM_OXE_IOI_PKTS_UNORDERED,
+	CXIDV_TELEM_OXE_MCU_MEAS_0,
+	CXIDV_TELEM_OXE_MCU_MEAS_1,
+	CXIDV_TELEM_OXE_MCU_MEAS_2,
+	CXIDV_TELEM_OXE_MCU_MEAS_3,
+	CXIDV_TELEM_OXE_MCU_MEAS_4,
+	CXIDV_TELEM_OXE_MCU_MEAS_5,
+	CXIDV_TELEM_OXE_MCU_MEAS_6,
+	CXIDV_TELEM_OXE_MCU_MEAS_7,
+	CXIDV_TELEM_OXE_MCU_MEAS_8,
+	CXIDV_TELEM_OXE_MCU_MEAS_9,
+	CXIDV_TELEM_OXE_MCU_MEAS_10,
+	CXIDV_TELEM_OXE_MCU_MEAS_11,
+	CXIDV_TELEM_OXE_MCU_MEAS_12,
+	CXIDV_TELEM_OXE_MCU_MEAS_13,
+	CXIDV_TELEM_OXE_MCU_MEAS_14,
+	CXIDV_TELEM_OXE_MCU_MEAS_15,
+	CXIDV_TELEM_OXE_MCU_MEAS_16,
+	CXIDV_TELEM_OXE_MCU_MEAS_17,
+	CXIDV_TELEM_OXE_MCU_MEAS_18,
+	CXIDV_TELEM_OXE_MCU_MEAS_19,
+	CXIDV_TELEM_OXE_MCU_MEAS_20,
+	CXIDV_TELEM_OXE_MCU_MEAS_21,
+	CXIDV_TELEM_OXE_MCU_MEAS_22,
+	CXIDV_TELEM_OXE_MCU_MEAS_23,
+	CXIDV_TELEM_OXE_MCU_MEAS_24,
+	CXIDV_TELEM_OXE_MCU_MEAS_25,
+	CXIDV_TELEM_OXE_MCU_MEAS_26,
+	CXIDV_TELEM_OXE_MCU_MEAS_27,
+	CXIDV_TELEM_OXE_MCU_MEAS_28,
+	CXIDV_TELEM_OXE_MCU_MEAS_29,
+	CXIDV_TELEM_OXE_MCU_MEAS_30,
+	CXIDV_TELEM_OXE_MCU_MEAS_31,
+	CXIDV_TELEM_OXE_MCU_MEAS_32,
+	CXIDV_TELEM_OXE_MCU_MEAS_33,
+	CXIDV_TELEM_OXE_MCU_MEAS_34,
+	CXIDV_TELEM_OXE_MCU_MEAS_35,
+	CXIDV_TELEM_OXE_MCU_MEAS_36,
+	CXIDV_TELEM_OXE_MCU_MEAS_37,
+	CXIDV_TELEM_OXE_MCU_MEAS_38,
+	CXIDV_TELEM_OXE_MCU_MEAS_39,
+	CXIDV_TELEM_OXE_MCU_MEAS_40,
+	CXIDV_TELEM_OXE_MCU_MEAS_41,
+	CXIDV_TELEM_OXE_MCU_MEAS_42,
+	CXIDV_TELEM_OXE_MCU_MEAS_43,
+	CXIDV_TELEM_OXE_MCU_MEAS_44,
+	CXIDV_TELEM_OXE_MCU_MEAS_45,
+	CXIDV_TELEM_OXE_MCU_MEAS_46,
+	CXIDV_TELEM_OXE_MCU_MEAS_47,
+	CXIDV_TELEM_OXE_MCU_MEAS_48,
+	CXIDV_TELEM_OXE_MCU_MEAS_49,
+	CXIDV_TELEM_OXE_MCU_MEAS_50,
+	CXIDV_TELEM_OXE_MCU_MEAS_51,
+	CXIDV_TELEM_OXE_MCU_MEAS_52,
+	CXIDV_TELEM_OXE_MCU_MEAS_53,
+	CXIDV_TELEM_OXE_MCU_MEAS_54,
+	CXIDV_TELEM_OXE_MCU_MEAS_55,
+	CXIDV_TELEM_OXE_MCU_MEAS_56,
+	CXIDV_TELEM_OXE_MCU_MEAS_57,
+	CXIDV_TELEM_OXE_MCU_MEAS_58,
+	CXIDV_TELEM_OXE_MCU_MEAS_59,
+	CXIDV_TELEM_OXE_MCU_MEAS_60,
+	CXIDV_TELEM_OXE_MCU_MEAS_61,
+	CXIDV_TELEM_OXE_MCU_MEAS_62,
+	CXIDV_TELEM_OXE_MCU_MEAS_63,
+	CXIDV_TELEM_OXE_MCU_MEAS_64,
+	CXIDV_TELEM_OXE_MCU_MEAS_65,
+	CXIDV_TELEM_OXE_MCU_MEAS_66,
+	CXIDV_TELEM_OXE_MCU_MEAS_67,
+	CXIDV_TELEM_OXE_MCU_MEAS_68,
+	CXIDV_TELEM_OXE_MCU_MEAS_69,
+	CXIDV_TELEM_OXE_MCU_MEAS_70,
+	CXIDV_TELEM_OXE_MCU_MEAS_71,
+	CXIDV_TELEM_OXE_MCU_MEAS_72,
+	CXIDV_TELEM_OXE_MCU_MEAS_73,
+	CXIDV_TELEM_OXE_MCU_MEAS_74,
+	CXIDV_TELEM_OXE_MCU_MEAS_75,
+	CXIDV_TELEM_OXE_MCU_MEAS_76,
+	CXIDV_TELEM_OXE_MCU_MEAS_77,
+	CXIDV_TELEM_OXE_MCU_MEAS_78,
+	CXIDV_TELEM_OXE_MCU_MEAS_79,
+	CXIDV_TELEM_OXE_MCU_MEAS_80,
+	CXIDV_TELEM_OXE_MCU_MEAS_81,
+	CXIDV_TELEM_OXE_MCU_MEAS_82,
+	CXIDV_TELEM_OXE_MCU_MEAS_83,
+	CXIDV_TELEM_OXE_MCU_MEAS_84,
+	CXIDV_TELEM_OXE_MCU_MEAS_85,
+	CXIDV_TELEM_OXE_MCU_MEAS_86,
+	CXIDV_TELEM_OXE_MCU_MEAS_87,
+	CXIDV_TELEM_OXE_MCU_MEAS_88,
+	CXIDV_TELEM_OXE_MCU_MEAS_89,
+	CXIDV_TELEM_OXE_MCU_MEAS_90,
+	CXIDV_TELEM_OXE_MCU_MEAS_91,
+	CXIDV_TELEM_OXE_MCU_MEAS_92,
+	CXIDV_TELEM_OXE_MCU_MEAS_93,
+	CXIDV_TELEM_OXE_MCU_MEAS_94,
+	CXIDV_TELEM_OXE_MCU_MEAS_95,
+	CXIDV_TELEM_OXE_MEM_COR_ERR_CNTR,
+	CXIDV_TELEM_OXE_MEM_UCOR_ERR_CNTR,
+	CXIDV_TELEM_OXE_NUM_HRP_CMDS,
+	CXIDV_TELEM_OXE_PRF_SET0_OCC_HIST_BIN0,
+	CXIDV_TELEM_OXE_PRF_SET0_OCC_HIST_BIN1,
+	CXIDV_TELEM_OXE_PRF_SET0_OCC_HIST_BIN2,
+	CXIDV_TELEM_OXE_PRF_SET0_OCC_HIST_BIN3,
+	CXIDV_TELEM_OXE_PRF_SET0_PKTBUF_NA,
+	CXIDV_TELEM_OXE_PRF_SET0_SMT_NA,
+	CXIDV_TELEM_OXE_PRF_SET0_SPT_NA,
+	CXIDV_TELEM_OXE_PRF_SET0_SRB_NA,
+	CXIDV_TELEM_OXE_PRF_SET0_ST_DMA_MDR,
+	CXIDV_TELEM_OXE_PRF_SET0_ST_DMA_UPD,
+	CXIDV_TELEM_OXE_PRF_SET0_ST_HEADER,
+	CXIDV_TELEM_OXE_PRF_SET0_ST_PCT_IDX_WAIT,
+	CXIDV_TELEM_OXE_PRF_SET0_ST_PKTBUF_GNT,
+	CXIDV_TELEM_OXE_PRF_SET0_ST_PKTBUF_REQ,
+	CXIDV_TELEM_OXE_PRF_SET0_ST_READY,
+	CXIDV_TELEM_OXE_PRF_SET0_TS_SELECT,
+	CXIDV_TELEM_OXE_PRF_SET1_OCC_HIST_BIN0,
+	CXIDV_TELEM_OXE_PRF_SET1_OCC_HIST_BIN1,
+	CXIDV_TELEM_OXE_PRF_SET1_OCC_HIST_BIN2,
+	CXIDV_TELEM_OXE_PRF_SET1_OCC_HIST_BIN3,
+	CXIDV_TELEM_OXE_PRF_SET1_PKTBUF_NA,
+	CXIDV_TELEM_OXE_PRF_SET1_SMT_NA,
+	CXIDV_TELEM_OXE_PRF_SET1_SPT_NA,
+	CXIDV_TELEM_OXE_PRF_SET1_SRB_NA,
+	CXIDV_TELEM_OXE_PRF_SET1_ST_DMA_MDR,
+	CXIDV_TELEM_OXE_PRF_SET1_ST_DMA_UPD,
+	CXIDV_TELEM_OXE_PRF_SET1_ST_HEADER,
+	CXIDV_TELEM_OXE_PRF_SET1_ST_PCT_IDX_WAIT,
+	CXIDV_TELEM_OXE_PRF_SET1_ST_PKTBUF_GNT,
+	CXIDV_TELEM_OXE_PRF_SET1_ST_PKTBUF_REQ,
+	CXIDV_TELEM_OXE_PRF_SET1_ST_READY,
+	CXIDV_TELEM_OXE_PRF_SET1_TS_SELECT,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_0,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_1,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_2,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_3,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_4,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_5,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_6,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_7,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_8,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_9,
+	CXIDV_TELEM_OXE_PTL_TX_MR_MSGS,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_0,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_1,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_2,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_3,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_4,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_5,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_6,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_7,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_8,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_9,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_0,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_1,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_2,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_3,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_4,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_5,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_6,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_7,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_8,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_9,
+	CXIDV_TELEM_OXE_SMT_CDT_ERRS,
+	CXIDV_TELEM_OXE_SPT_CDT_ERRS,
+	CXIDV_TELEM_OXE_STALL_FGFC_BLK_0,
+	CXIDV_TELEM_OXE_STALL_FGFC_BLK_1,
+	CXIDV_TELEM_OXE_STALL_FGFC_BLK_2,
+	CXIDV_TELEM_OXE_STALL_FGFC_BLK_3,
+	CXIDV_TELEM_OXE_STALL_FGFC_CNTRL_0,
+	CXIDV_TELEM_OXE_STALL_FGFC_CNTRL_1,
+	CXIDV_TELEM_OXE_STALL_FGFC_CNTRL_2,
+	CXIDV_TELEM_OXE_STALL_FGFC_CNTRL_3,
+	CXIDV_TELEM_OXE_STALL_FGFC_END_0,
+	CXIDV_TELEM_OXE_STALL_FGFC_END_1,
+	CXIDV_TELEM_OXE_STALL_FGFC_END_2,
+	CXIDV_TELEM_OXE_STALL_FGFC_END_3,
+	CXIDV_TELEM_OXE_STALL_FGFC_START_0,
+	CXIDV_TELEM_OXE_STALL_FGFC_START_1,
+	CXIDV_TELEM_OXE_STALL_FGFC_START_2,
+	CXIDV_TELEM_OXE_STALL_FGFC_START_3,
+	CXIDV_TELEM_OXE_STALL_HDR_ARB,
+	CXIDV_TELEM_OXE_STALL_IDC_CMD_NO_DEQ,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_0,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_1,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_2,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_3,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_4,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_5,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_6,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_7,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_8,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_9,
+	CXIDV_TELEM_OXE_STALL_IOI_LAST_ORDERED,
+	CXIDV_TELEM_OXE_STALL_NON_IDC_CMD_NO_DEQ,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_0,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_1,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_2,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_3,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_4,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_5,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_6,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_7,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_8,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_9,
+	CXIDV_TELEM_OXE_STALL_PCIE_SCOREBOARD,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_0,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_1,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_2,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_3,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_4,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_5,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_6,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_7,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_8,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_9,
+	CXIDV_TELEM_OXE_STALL_STFWD_EOP,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_0,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_1,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_2,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_3,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_4,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_5,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_6,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_7,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_8,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_9,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_0,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_1,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_2,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_3,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_4,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_5,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_6,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_7,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_8,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_9,
+	CXIDV_TELEM_OXE_STALL_WITH_NO_ATU_TAG,
+	CXIDV_TELEM_OXE_STALL_WITH_NO_PCI_TAG,
+	CXIDV_TELEM_OXE_STALL_WR_CONFLICT_PKT_BUFF_BNK_0,
+	CXIDV_TELEM_OXE_STALL_WR_CONFLICT_PKT_BUFF_BNK_1,
+	CXIDV_TELEM_OXE_STALL_WR_CONFLICT_PKT_BUFF_BNK_2,
+	CXIDV_TELEM_OXE_STALL_WR_CONFLICT_PKT_BUFF_BNK_3,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_0,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_1,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_2,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_3,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_4,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_5,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_6,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_7,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_8,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_9,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_0,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_1,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_2,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_3,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_4,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_5,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_6,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_7,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_8,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_9,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_0,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_1,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_2,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_3,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_4,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_5,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_6,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_7,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_8,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_9,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_0,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_1,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_2,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_3,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_4,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_5,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_6,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_7,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_8,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_9,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_10,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_11,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_12,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_13,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_14,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_15,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_16,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_17,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_18,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_19,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_20,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_21,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_22,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_23,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_24,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_25,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_26,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_27,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_28,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_29,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_30,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_31,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_32,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_33,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_34,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_35,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_36,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_37,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_38,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_39,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_40,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_41,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_42,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_43,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_44,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_45,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_46,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_47,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_48,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_49,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_50,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_51,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_52,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_53,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_54,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_55,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_56,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_57,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_58,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_59,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_60,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_61,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_62,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_63,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_64,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_65,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_66,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_67,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_68,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_69,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_70,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_71,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_72,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_73,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_74,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_75,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_76,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_77,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_78,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_79,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_80,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_81,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_82,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_83,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_84,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_85,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_86,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_87,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_88,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_89,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_90,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_91,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_92,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_93,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_94,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_95,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_0,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_1,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_2,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_3,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_4,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_5,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_6,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_7,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_8,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_9,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_10,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_11,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_12,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_13,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_14,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_15,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_16,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_17,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_18,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_19,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_20,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_21,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_22,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_23,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_24,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_25,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_26,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_27,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_28,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_29,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_30,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_31,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_32,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_33,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_34,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_35,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_36,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_37,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_38,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_39,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_40,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_41,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_42,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_43,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_44,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_45,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_46,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_47,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_48,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_49,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_50,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_51,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_52,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_53,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_54,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_55,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_56,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_57,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_58,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_59,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_60,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_61,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_62,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_63,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_64,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_65,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_66,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_67,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_68,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_69,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_70,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_71,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_72,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_73,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_74,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_75,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_76,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_77,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_78,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_79,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_80,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_81,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_82,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_83,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_84,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_85,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_86,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_87,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_88,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_89,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_90,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_91,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_92,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_93,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_94,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_95,
+};
+
+static const uint64_t set_parbs[] = {
+	CXIDV_TELEM_PARBS_RARB_ATU_COMPLETION_PKTS,
+	CXIDV_TELEM_PARBS_RARB_ATU_POSTED_PKTS,
+	CXIDV_TELEM_PARBS_RARB_CQ_COMPLETION_PKTS,
+	CXIDV_TELEM_PARBS_RARB_CQ_POSTED_PKTS,
+	CXIDV_TELEM_PARBS_RARB_EE_POSTED_PKTS,
+	CXIDV_TELEM_PARBS_RARB_IXE_COMPLETION_PKTS,
+	CXIDV_TELEM_PARBS_RARB_IXE_POSTED_PKTS,
+	CXIDV_TELEM_PARBS_RARB_OXE_COMPLETION_PKTS,
+	CXIDV_TELEM_PARBS_RARB_PI_COMPLETION_PKTS,
+	CXIDV_TELEM_PARBS_RARB_PI_MBE_CNT,
+	CXIDV_TELEM_PARBS_RARB_PI_POSTED_PKTS,
+	CXIDV_TELEM_PARBS_RARB_PI_SBE_CNT,
+	CXIDV_TELEM_PARBS_STS_CREDITS_IN_USE_TARB_PI_NON_POSTED_CREDITS,
+	CXIDV_TELEM_PARBS_STS_CREDITS_IN_USE_TARB_PI_POSTED_CREDITS,
+	CXIDV_TELEM_PARBS_TARB_ATU_MBE_CNT,
+	CXIDV_TELEM_PARBS_TARB_ATU_NON_POSTED_FIFO_MBE,
+	CXIDV_TELEM_PARBS_TARB_ATU_NON_POSTED_FIFO_SBE,
+	CXIDV_TELEM_PARBS_TARB_ATU_NON_POSTED_PKTS,
+	CXIDV_TELEM_PARBS_TARB_ATU_POSTED_FIFO_MBE,
+	CXIDV_TELEM_PARBS_TARB_ATU_POSTED_FIFO_SBE,
+	CXIDV_TELEM_PARBS_TARB_ATU_POSTED_PKTS,
+	CXIDV_TELEM_PARBS_TARB_ATU_SBE_CNT,
+	CXIDV_TELEM_PARBS_TARB_CQ_MBE_CNT,
+	CXIDV_TELEM_PARBS_TARB_CQ_NON_POSTED_FIFO_MBE,
+	CXIDV_TELEM_PARBS_TARB_CQ_NON_POSTED_FIFO_SBE,
+	CXIDV_TELEM_PARBS_TARB_CQ_NON_POSTED_PKTS,
+	CXIDV_TELEM_PARBS_TARB_CQ_POSTED_FIFO_MBE,
+	CXIDV_TELEM_PARBS_TARB_CQ_POSTED_FIFO_SBE,
+	CXIDV_TELEM_PARBS_TARB_CQ_POSTED_PKTS,
+	CXIDV_TELEM_PARBS_TARB_CQ_SBE_CNT,
+	CXIDV_TELEM_PARBS_TARB_EE_MBE_CNT,
+	CXIDV_TELEM_PARBS_TARB_EE_POSTED_FIFO_MBE,
+	CXIDV_TELEM_PARBS_TARB_EE_POSTED_FIFO_SBE,
+	CXIDV_TELEM_PARBS_TARB_EE_POSTED_PKTS,
+	CXIDV_TELEM_PARBS_TARB_EE_SBE_CNT,
+	CXIDV_TELEM_PARBS_TARB_IXE_MBE_CNT,
+	CXIDV_TELEM_PARBS_TARB_IXE_NON_POSTED_FIFO_MBE,
+	CXIDV_TELEM_PARBS_TARB_IXE_NON_POSTED_FIFO_SBE,
+	CXIDV_TELEM_PARBS_TARB_IXE_NON_POSTED_PKTS,
+	CXIDV_TELEM_PARBS_TARB_IXE_POSTED_FIFO_MBE,
+	CXIDV_TELEM_PARBS_TARB_IXE_POSTED_FIFO_SBE,
+	CXIDV_TELEM_PARBS_TARB_IXE_POSTED_PKTS,
+	CXIDV_TELEM_PARBS_TARB_IXE_SBE_CNT,
+	CXIDV_TELEM_PARBS_TARB_OXE_MBE_CNT,
+	CXIDV_TELEM_PARBS_TARB_OXE_NON_POSTED_FIFO_MBE,
+	CXIDV_TELEM_PARBS_TARB_OXE_NON_POSTED_FIFO_SBE,
+	CXIDV_TELEM_PARBS_TARB_OXE_NON_POSTED_PKTS,
+	CXIDV_TELEM_PARBS_TARB_OXE_SBE_CNT,
+	CXIDV_TELEM_PARBS_TARB_PI_NON_POSTED_BLOCKED_CNT,
+	CXIDV_TELEM_PARBS_TARB_PI_NON_POSTED_PKTS,
+	CXIDV_TELEM_PARBS_TARB_PI_POSTED_BLOCKED_CNT,
+	CXIDV_TELEM_PARBS_TARB_PI_POSTED_PKTS,
+};
+
+static const uint64_t set_pct[] = {
+	CXIDV_TELEM_PCT_ACCEL_CLOSE,
+	CXIDV_TELEM_PCT_BAD_SEQ_NACKS,
+	CXIDV_TELEM_PCT_CLEAR_CLOSE_DROP,
+	CXIDV_TELEM_PCT_CLEAR_SENT,
+	CXIDV_TELEM_PCT_CLOSE_RSP_DROPS,
+	CXIDV_TELEM_PCT_CLOSE_SENT,
+	CXIDV_TELEM_PCT_CLR_CLS_STALLS,
+	CXIDV_TELEM_PCT_CLS_REQ_BAD_SEQNO_DROPS,
+	CXIDV_TELEM_PCT_CLS_REQ_MISS_TCT,
+	CXIDV_TELEM_PCT_CONN_SCT_OPEN,
+	CXIDV_TELEM_PCT_CONN_TCT_OPEN,
+	CXIDV_TELEM_PCT_ERR_NO_MATCHING_MST,
+	CXIDV_TELEM_PCT_ERR_NO_MATCHING_TRS,
+	CXIDV_TELEM_PCT_ETH_PACKETS,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_0,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_1,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_2,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_3,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_4,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_5,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_6,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_7,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_8,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_9,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_10,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_11,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_12,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_13,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_14,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_15,
+	CXIDV_TELEM_PCT_HRP_RESPONSES_RECEIVED,
+	CXIDV_TELEM_PCT_HRP_RSP_DISCARD_RECEIVED,
+	CXIDV_TELEM_PCT_HRP_RSP_ERR_RECEIVED,
+	CXIDV_TELEM_PCT_MEM_COR_ERR_CNTR,
+	CXIDV_TELEM_PCT_MEM_UCOR_ERR_CNTR,
+	CXIDV_TELEM_PCT_MST_HIT_ON_SOM,
+	CXIDV_TELEM_PCT_NO_MATCHING_TCT,
+	CXIDV_TELEM_PCT_NO_MST_NACKS,
+	CXIDV_TELEM_PCT_NO_TCT_NACKS,
+	CXIDV_TELEM_PCT_NO_TRS_NACKS,
+	CXIDV_TELEM_PCT_OPTIP_PACKETS,
+	CXIDV_TELEM_PCT_PCT_CQ_NOTIFICATIONS,
+	CXIDV_TELEM_PCT_PCT_CQ_STALLS,
+	CXIDV_TELEM_PCT_PCT_EE_EVENTS,
+	CXIDV_TELEM_PCT_PCT_EE_STALLS,
+	CXIDV_TELEM_PCT_PCT_HNI_FLITS,
+	CXIDV_TELEM_PCT_PCT_HNI_STALLS,
+	CXIDV_TELEM_PCT_PCT_MST_CMD0,
+	CXIDV_TELEM_PCT_PCT_MST_CMD1,
+	CXIDV_TELEM_PCT_PCT_MST_STALLS0,
+	CXIDV_TELEM_PCT_PCT_MST_STALLS1,
+	CXIDV_TELEM_PCT_PRF_MST_STATUS_MAX_MST_IN_USE,
+	CXIDV_TELEM_PCT_PRF_MST_STATUS_MST_IN_USE,
+	CXIDV_TELEM_PCT_PRF_SCT_STATUS_MAX_SCT_IN_USE,
+	CXIDV_TELEM_PCT_PRF_SCT_STATUS_SCT_IN_USE,
+	CXIDV_TELEM_PCT_PRF_SMT_STATUS_MAX_SMT_IN_USE,
+	CXIDV_TELEM_PCT_PRF_SMT_STATUS_SMT_IN_USE,
+	CXIDV_TELEM_PCT_PRF_SPT_STATUS_MAX_SPT_IN_USE,
+	CXIDV_TELEM_PCT_PRF_SPT_STATUS_SPT_IN_USE,
+	CXIDV_TELEM_PCT_PRF_SRB_STATUS_MAX_SRB_IN_USE,
+	CXIDV_TELEM_PCT_PRF_SRB_STATUS_SRB_IN_USE,
+	CXIDV_TELEM_PCT_PRF_TCT_STATUS_MAX_TCT_IN_USE,
+	CXIDV_TELEM_PCT_PRF_TCT_STATUS_TCT_IN_USE,
+	CXIDV_TELEM_PCT_PRF_TRS_STATUS_MAX_TRS_IN_USE,
+	CXIDV_TELEM_PCT_PRF_TRS_STATUS_TRS_IN_USE,
+	CXIDV_TELEM_PCT_PTLS_RESPONSE,
+	CXIDV_TELEM_PCT_REQ_BLOCKED_CLEARING,
+	CXIDV_TELEM_PCT_REQ_BLOCKED_CLOSING,
+	CXIDV_TELEM_PCT_REQ_BLOCKED_RETRY,
+	CXIDV_TELEM_PCT_REQ_NO_RESPONSE,
+	CXIDV_TELEM_PCT_REQ_ORDERED,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_0,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_1,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_2,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_3,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_4,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_5,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_6,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_7,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_8,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_9,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_10,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_11,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_12,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_13,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_14,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_15,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_16,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_17,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_18,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_19,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_20,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_21,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_22,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_23,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_24,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_25,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_26,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_27,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_28,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_29,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_30,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_31,
+	CXIDV_TELEM_PCT_REQ_SRC_ERROR,
+	CXIDV_TELEM_PCT_REQ_TCT_TMOUT_DROPS,
+	CXIDV_TELEM_PCT_REQ_UNORDERED,
+	CXIDV_TELEM_PCT_RESOURCE_BUSY,
+	CXIDV_TELEM_PCT_RESPONSES_RECEIVED,
+	CXIDV_TELEM_PCT_RETRY_MST_GET,
+	CXIDV_TELEM_PCT_RETRY_SRB_REQUESTS,
+	CXIDV_TELEM_PCT_RETRY_TRS_PUT,
+	CXIDV_TELEM_PCT_RSP_DROPPED_CLS_TRY,
+	CXIDV_TELEM_PCT_RSP_DROPPED_INACTIVE,
+	CXIDV_TELEM_PCT_RSP_DROPPED_TIMEOUT,
+	CXIDV_TELEM_PCT_RSP_DROPPED_TRY,
+	CXIDV_TELEM_PCT_RSP_ERR_RCVD,
+	CXIDV_TELEM_PCT_SCT_STALL_STATE,
+	CXIDV_TELEM_PCT_SCT_TIMEOUTS,
+	CXIDV_TELEM_PCT_SPT_TIMEOUTS,
+	CXIDV_TELEM_PCT_TCT_TIMEOUTS,
+	CXIDV_TELEM_PCT_TGT_CLS_ABORT,
+	CXIDV_TELEM_PCT_TRS_HIT_ON_REQ,
+	CXIDV_TELEM_PCT_TRS_REPLAY_PEND_DROPS,
+	CXIDV_TELEM_PCT_TRS_RSP_NACK_DROPS,
+};
+
+static const uint64_t set_pi[] = {
+	CXIDV_TELEM_PI_DMAC_AXI_RD_REQUESTS,
+	CXIDV_TELEM_PI_DMAC_AXI_RD_RSP_DECERRS,
+	CXIDV_TELEM_PI_DMAC_AXI_RD_RSP_PARERRS,
+	CXIDV_TELEM_PI_DMAC_AXI_RD_RSP_SLVERRS,
+	CXIDV_TELEM_PI_DMAC_CE_MWR_TLPS,
+	CXIDV_TELEM_PI_DMAC_DESC_COR_ERRORS,
+	CXIDV_TELEM_PI_DMAC_DESC_UCOR_ERRORS,
+	CXIDV_TELEM_PI_DMAC_IRQS,
+	CXIDV_TELEM_PI_DMAC_PAYLOAD_MWR_TLPS,
+	CXIDV_TELEM_PI_IPD_CFG_EVENT_CNTS_OVF_CNT,
+	CXIDV_TELEM_PI_IPD_DBIC_DBI_ACKS,
+	CXIDV_TELEM_PI_IPD_DBIC_DBI_REQUESTS,
+	CXIDV_TELEM_PI_IPD_DMAC_P_FIFO_COR_ERRORS,
+	CXIDV_TELEM_PI_IPD_DMAC_P_FIFO_UCOR_ERRORS,
+	CXIDV_TELEM_PI_IPD_IPD_TRIGGER_EVENTS_0,
+	CXIDV_TELEM_PI_IPD_IPD_TRIGGER_EVENTS_1,
+	CXIDV_TELEM_PI_IPD_MSIXC_IB_IRQ_PBAS,
+	CXIDV_TELEM_PI_IPD_MSIXC_IB_IRQS_DISCARDED,
+	CXIDV_TELEM_PI_IPD_MSIXC_IB_IRQS_SENT,
+	CXIDV_TELEM_PI_IPD_MSIXC_IB_LEGACY_IRQS_SENT,
+	CXIDV_TELEM_PI_IPD_MSIXC_OOB_IRQ_PBAS,
+	CXIDV_TELEM_PI_IPD_MSIXC_OOB_IRQS_DISCARDED,
+	CXIDV_TELEM_PI_IPD_MSIXC_OOB_IRQS_SENT,
+	CXIDV_TELEM_PI_IPD_MSIXC_OOB_LEGACY_IRQS_SENT,
+	CXIDV_TELEM_PI_IPD_MSIXC_PBA_COR_ERRORS,
+	CXIDV_TELEM_PI_IPD_MSIXC_PBA_UCOR_ERRORS,
+	CXIDV_TELEM_PI_IPD_MSIXC_PTI_FIFO_COR_ERRORS,
+	CXIDV_TELEM_PI_IPD_MSIXC_PTI_FIFO_UCOR_ERRORS,
+	CXIDV_TELEM_PI_IPD_MSIXC_TABLE_COR_ERRORS,
+	CXIDV_TELEM_PI_IPD_MSIXC_TABLE_UCOR_ERRORS,
+	CXIDV_TELEM_PI_IPD_PRI_RBYP_DATA_PARITY_ERRORS,
+	CXIDV_TELEM_PI_IPD_PRI_RBYP_HDR_PARITY_ERRORS,
+	CXIDV_TELEM_PI_IPD_PRI_RBYP_TLPS,
+	CXIDV_TELEM_PI_IPD_PRI_RBYP_TLPS_ABORTED,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_BLOCKED_ON_MB,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_BLOCKED_ON_RARB,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_DATA_PARITY_ERRORS,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_HDR_PARITY_ERRORS,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_MRD_TLPS,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_MSG_TLPS,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_MSGD_TLPS,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_MWR_TLPS,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_TLPS,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_TLPS_ABORTED,
+	CXIDV_TELEM_PI_IPD_PTI_DBG_BLOCKED_ON_NPH_CRD,
+	CXIDV_TELEM_PI_IPD_PTI_DBG_BLOCKED_ON_PD_CRD,
+	CXIDV_TELEM_PI_IPD_PTI_DBG_BLOCKED_ON_PH_CRD,
+	CXIDV_TELEM_PI_IPD_PTI_DBG_BLOCKED_ON_TAG,
+	CXIDV_TELEM_PI_IPD_PTI_DBG_XALI_NON_POSTED_TLPS,
+	CXIDV_TELEM_PI_IPD_PTI_DBG_XALI_POSTED_TLPS,
+	CXIDV_TELEM_PI_IPD_PTI_DMAC_BLOCKED_ON_PD_CRD,
+	CXIDV_TELEM_PI_IPD_PTI_DMAC_BLOCKED_ON_PH_CRD,
+	CXIDV_TELEM_PI_IPD_PTI_DMAC_XALI_POSTED_TLPS,
+	CXIDV_TELEM_PI_IPD_PTI_MSIXC_BLOCKED_ON_PD_CRD,
+	CXIDV_TELEM_PI_IPD_PTI_MSIXC_BLOCKED_ON_PH_CRD,
+	CXIDV_TELEM_PI_IPD_PTI_MSIXC_FIFO_COR_ERRORS,
+	CXIDV_TELEM_PI_IPD_PTI_MSIXC_FIFO_UCOR_ERRORS,
+	CXIDV_TELEM_PI_IPD_PTI_MSIXC_XALI_POSTED_TLPS,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_BLOCKED_ON_NPD_CRD,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_BLOCKED_ON_NPH_CRD,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_BLOCKED_ON_PD_CRD,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_BLOCKED_ON_PH_CRD,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_BLOCKED_ON_TAG,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_CMPL_TO,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_CMPL_TO_FIFO_COR_ERRORS,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_CMPL_TO_FIFO_UCOR_ERRORS,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_NP_FIFO_COR_ERRORS,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_NP_FIFO_UCOR_ERRORS,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_P_FIFO_COR_ERRORS,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_P_FIFO_UCOR_ERRORS,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_XALI_NON_POSTED_TLPS,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_XALI_POSTED_TLPS,
+	CXIDV_TELEM_PI_PRI_MB_AXI_RD_REQUESTS,
+	CXIDV_TELEM_PI_PRI_MB_AXI_RD_RSP_DECERRS,
+	CXIDV_TELEM_PI_PRI_MB_AXI_RD_RSP_PARERRS,
+	CXIDV_TELEM_PI_PRI_MB_AXI_RD_RSP_SLVERRS,
+	CXIDV_TELEM_PI_PRI_MB_AXI_WR_REQUESTS,
+	CXIDV_TELEM_PI_PRI_MB_AXI_WR_RSP_DECERRS,
+	CXIDV_TELEM_PI_PRI_MB_AXI_WR_RSP_SLVERRS,
+	CXIDV_TELEM_PI_PRI_MB_RTRGT_FIFO_COR_ERRORS,
+	CXIDV_TELEM_PI_PRI_MB_RTRGT_FIFO_UCOR_ERRORS,
+	CXIDV_TELEM_PI_PRI_MB_RTRGT_MRD_TLPS,
+	CXIDV_TELEM_PI_PRI_MB_RTRGT_MWR_TLPS,
+	CXIDV_TELEM_PI_PRI_MB_RTRGT_NON_POSTED_TLP_DISCARDS,
+	CXIDV_TELEM_PI_PRI_MB_RTRGT_POSTED_TLP_DISCARDS,
+	CXIDV_TELEM_PI_PRI_MB_RTRGT_POSTED_TLP_PARTIAL_DISCARDS,
+	CXIDV_TELEM_PI_PRI_MB_RTRGT_TLP_DISCARDS,
+	CXIDV_TELEM_PI_PRI_MB_RTRGT_TLPS,
+	CXIDV_TELEM_PI_PRI_MB_XALI_CMPL_CA_TLPS,
+	CXIDV_TELEM_PI_PRI_MB_XALI_CMPL_TLPS,
+	CXIDV_TELEM_PI_PRI_MB_XALI_CMPL_UR_TLPS,
+	CXIDV_TELEM_PI_PRI_RARB_RBYP_FIFO_COR_ERRORS,
+	CXIDV_TELEM_PI_PRI_RARB_RBYP_FIFO_UCOR_ERRORS,
+	CXIDV_TELEM_PI_PRI_RARB_RBYP_TLP_DISCARDS,
+	CXIDV_TELEM_PI_PRI_RARB_RBYP_TLPS,
+	CXIDV_TELEM_PI_PRI_RARB_RTRGT_FIFO_COR_ERRORS,
+	CXIDV_TELEM_PI_PRI_RARB_RTRGT_FIFO_UCOR_ERRORS,
+	CXIDV_TELEM_PI_PRI_RARB_RTRGT_MSG_TLPS,
+	CXIDV_TELEM_PI_PRI_RARB_RTRGT_MSGD_TLPS,
+	CXIDV_TELEM_PI_PRI_RARB_RTRGT_MWR_TLPS,
+	CXIDV_TELEM_PI_PRI_RARB_RTRGT_TLP_DISCARDS,
+	CXIDV_TELEM_PI_PRI_RARB_RTRGT_TLPS,
+	CXIDV_TELEM_PI_PRI_RARB_SRIOVT_COR_ERRORS,
+	CXIDV_TELEM_PI_PRI_RARB_SRIOVT_UCOR_ERRORS,
+	CXIDV_TELEM_PI_PTI_TARB_ACXT_COR_ERRORS,
+	CXIDV_TELEM_PI_PTI_TARB_ACXT_UCOR_ERRORS,
+	CXIDV_TELEM_PI_PTI_TARB_AMO_PKTS,
+	CXIDV_TELEM_PI_PTI_TARB_DATA_COR_ERRORS,
+	CXIDV_TELEM_PI_PTI_TARB_DATA_UCOR_ERROR,
+	CXIDV_TELEM_PI_PTI_TARB_FETCHING_AMO_PKTS,
+	CXIDV_TELEM_PI_PTI_TARB_FLUSH_PKTS,
+	CXIDV_TELEM_PI_PTI_TARB_HDR_COR_ERRORS,
+	CXIDV_TELEM_PI_PTI_TARB_HDR_UCOR_ERRORS,
+	CXIDV_TELEM_PI_PTI_TARB_INV_RSP_PKTS,
+	CXIDV_TELEM_PI_PTI_TARB_IRQ_PKTS,
+	CXIDV_TELEM_PI_PTI_TARB_MRD_PKTS,
+	CXIDV_TELEM_PI_PTI_TARB_MWR_PKTS,
+	CXIDV_TELEM_PI_PTI_TARB_PG_REQ_PKTS,
+	CXIDV_TELEM_PI_PTI_TARB_PKT_DISCARDS,
+	CXIDV_TELEM_PI_PTI_TARB_PKTS,
+	CXIDV_TELEM_PI_PTI_TARB_RARB_CA_PKTS,
+	CXIDV_TELEM_PI_PTI_TARB_TRANSLATION_PKTS,
+};
+
+static const uint64_t set_rmu[] = {
+	CXIDV_TELEM_RMU_ENET_FRAME_REJECTED_CNTR, CXIDV_TELEM_RMU_ENET_PTLTE_SET_CTRL_ERR_CNTR,
+	CXIDV_TELEM_RMU_ENET_SUCCESS_CNTR,	  CXIDV_TELEM_RMU_MEM_COR_ERR_CNTR,
+	CXIDV_TELEM_RMU_MEM_UCOR_ERR_CNTR,	  CXIDV_TELEM_RMU_PTL_INVLD_DFA_CNTR,
+	CXIDV_TELEM_RMU_PTL_INVLD_VNI_CNTR,	  CXIDV_TELEM_RMU_PTL_NO_PTLTE_CNTR,
+	CXIDV_TELEM_RMU_PTL_SUCCESS_CNTR,
+};
+
+static const uint64_t set_tou[] = {
+	CXIDV_TELEM_TOU_CMD_FIFO_FULL_CYCLES, CXIDV_TELEM_TOU_CQ_TOU_NUM_CMDS,
+	CXIDV_TELEM_TOU_CQ_TOU_NUM_STALLS,    CXIDV_TELEM_TOU_CT_CMD_COUNTS_0,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_1,      CXIDV_TELEM_TOU_CT_CMD_COUNTS_2,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_3,      CXIDV_TELEM_TOU_CT_CMD_COUNTS_4,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_5,      CXIDV_TELEM_TOU_CT_CMD_COUNTS_6,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_7,      CXIDV_TELEM_TOU_CT_CMD_COUNTS_8,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_9,      CXIDV_TELEM_TOU_CT_CMD_COUNTS_10,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_11,     CXIDV_TELEM_TOU_CT_CMD_COUNTS_12,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_13,     CXIDV_TELEM_TOU_CT_CMD_COUNTS_14,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_15,     CXIDV_TELEM_TOU_FAIL_CNTR,
+	CXIDV_TELEM_TOU_LIST_REBUILD_CYCLES,  CXIDV_TELEM_TOU_NUM_CT_UPDATES,
+	CXIDV_TELEM_TOU_NUM_DOORBELL_WRITES,  CXIDV_TELEM_TOU_NUM_LIST_REBUILDS_0,
+	CXIDV_TELEM_TOU_NUM_LIST_REBUILDS_1,  CXIDV_TELEM_TOU_NUM_LIST_REBUILDS_2,
+	CXIDV_TELEM_TOU_NUM_LIST_REBUILDS_3,  CXIDV_TELEM_TOU_NUM_TRIG_CMDS_0,
+	CXIDV_TELEM_TOU_NUM_TRIG_CMDS_1,      CXIDV_TELEM_TOU_NUM_TRIG_CMDS_2,
+	CXIDV_TELEM_TOU_NUM_TRIG_CMDS_3,      CXIDV_TELEM_TOU_SUCCESS_CNTR,
+	CXIDV_TELEM_TOU_TOU_OXE_NUM_FLITS,    CXIDV_TELEM_TOU_TOU_OXE_NUM_IDLES,
+	CXIDV_TELEM_TOU_TOU_OXE_NUM_STALLS,
+};
+
+static const struct {
+	const uint64_t *items;
+	uint32_t count;
+} telem_sets[CXIDV_TELEM_SET_COUNT] = {
+	[CXIDV_TELEM_SET_ETHTOOL] = { set_ethtool, ARRAY_SIZE(set_ethtool) },
+	[CXIDV_TELEM_SET_ATU] = { set_atu, ARRAY_SIZE(set_atu) },
+	[CXIDV_TELEM_SET_CQ] = { set_cq, ARRAY_SIZE(set_cq) },
+	[CXIDV_TELEM_SET_EE] = { set_ee, ARRAY_SIZE(set_ee) },
+	[CXIDV_TELEM_SET_HNI] = { set_hni, ARRAY_SIZE(set_hni) },
+	[CXIDV_TELEM_SET_IXE] = { set_ixe, ARRAY_SIZE(set_ixe) },
+	[CXIDV_TELEM_SET_LPE] = { set_lpe, ARRAY_SIZE(set_lpe) },
+	[CXIDV_TELEM_SET_MB] = { set_mb, ARRAY_SIZE(set_mb) },
+	[CXIDV_TELEM_SET_MST] = { set_mst, ARRAY_SIZE(set_mst) },
+	[CXIDV_TELEM_SET_OXE] = { set_oxe, ARRAY_SIZE(set_oxe) },
+	[CXIDV_TELEM_SET_PARBS] = { set_parbs, ARRAY_SIZE(set_parbs) },
+	[CXIDV_TELEM_SET_PCT] = { set_pct, ARRAY_SIZE(set_pct) },
+	[CXIDV_TELEM_SET_PI] = { set_pi, ARRAY_SIZE(set_pi) },
+	[CXIDV_TELEM_SET_RMU] = { set_rmu, ARRAY_SIZE(set_rmu) },
+	[CXIDV_TELEM_SET_TOU] = { set_tou, ARRAY_SIZE(set_tou) },
+};
+
+const char *cxidv_telem_name(uint32_t item)
+{
+	return item < CXIDV_TELEM_COUNT ? telem_names[item] : NULL;
+}
+
+int cxidv_telem_lookup(const char *name)
+{
+	uint32_t i;
+
+	if (!name)
+		return -1;
+	for (i = 0; i < CXIDV_TELEM_COUNT; i++)
+		if (!strcmp(telem_names[i], name))
+			return i;
+	return -1;
+}
+
+int cxidv_telem_get_set(enum cxidv_telem_set set, const uint64_t **items, uint32_t *count)
+{
+	if ((unsigned int)set >= CXIDV_TELEM_SET_COUNT || !items || !count)
+		return EINVAL;
+	*items = telem_sets[set].items;
+	*count = telem_sets[set].count;
+	return 0;
+}
diff --git a/providers/cxi/cxidv.h b/providers/cxi/cxidv.h
new file mode 100644
index 000000000000..1d9bb428e257
--- /dev/null
+++ b/providers/cxi/cxidv.h
@@ -0,0 +1,418 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright 2026 Hewlett Packard Enterprise Development LP
+ */
+
+/*
+ * Direct-verbs extension for the CXI provider.
+ *
+ * Standard ibv_query_device()/ibv_query_device_ex() cover the generic
+ * device attributes (max_qp, max_cq, vendor_id, ...). CXI has additional
+ * device-wide HW properties (NIC address, PID space geometry, resource
+ * counts, ...) with no standard ibverbs equivalent; this header exposes
+ * those, mirroring the mlx5dv.h / efadv.h pattern used by other rdma-core
+ * providers for vendor-specific data.
+ */
+
+#ifndef __CXIDV_H__
+#define __CXIDV_H__
+
+#include <stdint.h>
+#include <infiniband/verbs.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct cxidv_lni {
+	struct ibv_context *context;
+	uint32_t handle;
+	uint32_t id;
+	uint32_t svc_id;
+};
+
+enum cxidv_pid_flags {
+	CXIDV_PID_ABSOLUTE = 1U << 0,
+};
+
+enum cxidv_svc_flags {
+	CXIDV_SVC_LIMITS = 1U << 0,
+	CXIDV_SVC_CREATE_TC = 1U << 1,
+	CXIDV_SVC_ENABLED = 1U << 2,
+};
+
+enum cxidv_svc_resource {
+	CXIDV_SVC_PTES,
+	CXIDV_SVC_TXQS,
+	CXIDV_SVC_TGQS,
+	CXIDV_SVC_EQS,
+	CXIDV_SVC_CTS,
+	CXIDV_SVC_ACS,
+	CXIDV_SVC_TLES,
+	CXIDV_SVC_LES,
+	CXIDV_SVC_RSRC_COUNT,
+};
+
+#define CXIDV_SVC_MAX_VNIS 4
+
+struct cxidv_svc_attr {
+	uint32_t svc_id;
+	/* Reserved; must be zero. */
+	uint16_t vni_min;
+	uint16_t vni_max;
+	/* Exact-list length; zero means system-empty or is_range. */
+	uint32_t vni_count;
+	/* System service requires CAP_SYS_ADMIN; allocation svc_id is zero. */
+	uint32_t is_system_svc;
+	/* Inclusive range endpoints are carried in vnis[0] and vnis[1]. */
+	uint32_t is_range;
+	uint16_t vnis[CXIDV_SVC_MAX_VNIS];
+	uint32_t tc_mask;
+	uint32_t uid;
+	uint32_t flags;
+	uint16_t maximum[CXIDV_SVC_RSRC_COUNT];
+	uint16_t reserved[CXIDV_SVC_RSRC_COUNT];
+};
+
+int cxidv_alloc_svc(struct ibv_context *context, const struct cxidv_svc_attr *attr,
+		    uint32_t *svc_id);
+int cxidv_query_svc(struct ibv_context *context, uint32_t svc_id, struct cxidv_svc_attr *attr);
+
+struct cxidv_svc_rsrc_use {
+	uint32_t svc_id;
+	uint32_t tle_pool_id;
+	uint16_t in_use[CXIDV_SVC_RSRC_COUNT];
+};
+
+int cxidv_get_svc_rsrc_use(struct ibv_context *context, uint32_t svc_id,
+			   struct cxidv_svc_rsrc_use *usage);
+int cxidv_get_svc_lpr(struct ibv_context *context, uint32_t svc_id, uint32_t *lpr);
+int cxidv_destroy_svc(struct ibv_context *context, uint32_t svc_id);
+int cxidv_enable_svc(struct ibv_context *context, uint32_t svc_id, int enable);
+int cxidv_svc_is_enabled(struct ibv_context *context, uint32_t svc_id, int *enable);
+
+enum cxidv_traffic_class {
+	CXIDV_TC_DEDICATED_ACCESS,
+	CXIDV_TC_LOW_LATENCY,
+	CXIDV_TC_BULK_DATA,
+	CXIDV_TC_BEST_EFFORT,
+	CXIDV_TC_ETH,
+};
+
+int cxidv_alloc_lni(struct ibv_context *context, uint32_t svc_id, struct cxidv_lni **lni);
+int cxidv_destroy_lni(struct cxidv_lni *lni);
+struct ibv_pd *cxidv_alloc_pd(struct cxidv_lni *lni);
+
+struct cxidv_cp {
+	struct cxidv_lni *lni;
+	uint32_t handle;
+	uint32_t vni;
+	uint32_t tc;
+	uint32_t type;
+	uint32_t lcid;
+};
+
+int cxidv_alloc_cp(struct cxidv_lni *lni, uint32_t vni, uint32_t tc, uint32_t type,
+		   struct cxidv_cp **out);
+int cxidv_destroy_cp(struct cxidv_cp *cp);
+
+struct cxidv_ct {
+	struct cxidv_lni *lni;
+	uint32_t handle;
+	uint32_t ctn;
+	void *writeback;
+	size_t writeback_size;
+	uint64_t writeback_offset;
+	void *doorbell;
+	size_t doorbell_size;
+};
+
+int cxidv_alloc_ct(struct cxidv_lni *lni, struct cxidv_ct **out);
+int cxidv_inbound_wait(struct ibv_context *context);
+int cxidv_alloc_ct_writeback(struct cxidv_lni *lni, void *writeback, struct cxidv_ct **out);
+int cxidv_destroy_ct(struct cxidv_ct *ct);
+
+struct cxidv_cmdq {
+	struct cxidv_lni *lni;
+	uint32_t handle;
+	uint32_t count;
+	uint32_t index;
+	void *commands;
+	size_t commands_size;
+	uint64_t commands_offset;
+	void *doorbell;
+	size_t doorbell_size;
+};
+
+int cxidv_alloc_cmdq(struct cxidv_lni *lni, uint32_t count, struct cxidv_cmdq **out);
+int cxidv_alloc_trigger_cmdq(struct cxidv_lni *lni, uint32_t count, struct cxidv_cmdq **out);
+int cxidv_destroy_cmdq(struct cxidv_cmdq *cmdq);
+
+struct cxidv_wait {
+	struct cxidv_lni *lni;
+	int fd;
+	/* Library-managed usage count; applications must treat this as read-only. */
+	unsigned int users;
+};
+
+/*
+ * A wait object remains valid until cxidv_destroy_wait() succeeds.
+ *
+ * If another object still references the wait, or another thread is creating
+ * such a reference, cxidv_destroy_wait() returns EBUSY and does not close/free
+ * the wait object. Callers may retry destroy after dependent objects are
+ * destroyed.
+ *
+ * Callers must prevent new operations using this pointer from starting while
+ * final destruction is in progress; a raw pointer cannot protect an operation
+ * that has not yet acquired its library-managed reference.
+ */
+int cxidv_alloc_wait(struct cxidv_lni *lni, struct cxidv_wait **out);
+int cxidv_destroy_wait(struct cxidv_wait *wait);
+
+enum cxidv_eq_flags {
+	CXIDV_EQ_REGISTER_PCT = 1U << 0,
+	CXIDV_EQ_PASSTHROUGH = 1U << 1,
+};
+
+struct cxidv_eq_attr {
+	void *queue;
+	size_t length;
+	uint32_t threshold_base;
+	uint32_t threshold_delta;
+	uint32_t threshold_count;
+	uint32_t ec_delay;
+	uint32_t cpu;
+	uint32_t reserved_slots;
+	uint32_t flags;
+	struct cxidv_wait *event_wait;
+	struct cxidv_wait *status_wait;
+};
+
+struct cxidv_eq {
+	struct cxidv_lni *lni;
+	struct cxidv_wait *event_wait;
+	struct cxidv_wait *status_wait;
+	uint32_t handle;
+	uint32_t eqn;
+	void *doorbell;
+	size_t doorbell_size;
+};
+
+int cxidv_alloc_eq(struct cxidv_lni *lni, struct ibv_mr *mr, const struct cxidv_eq_attr *attr,
+		   struct cxidv_eq **out);
+int cxidv_destroy_eq(struct cxidv_eq *eq);
+
+struct cxidv_csr {
+	struct ibv_context *context;
+	uint32_t handle;
+	void *address;
+	size_t length;
+	uint64_t mmap_offset;
+};
+
+int cxidv_map_csrs(struct ibv_context *context, struct cxidv_csr **out);
+int cxidv_unmap_csrs(struct cxidv_csr *csr);
+int cxidv_read_csr(const struct cxidv_csr *csr, uint64_t offset, void *value, size_t length);
+int cxidv_write_csr(const struct cxidv_csr *csr, uint64_t offset, const void *value, size_t length);
+int cxidv_write8_csr(const struct cxidv_csr *csr, uint64_t offset, uint8_t value);
+
+int cxidv_alloc_pid(struct ibv_pd *pd, uint32_t flags, uint32_t *pid);
+int cxidv_query_pid(struct ibv_pd *pd, uint32_t *pid);
+
+enum cxidv_cassini_version {
+	CXIDV_CASSINI_1_0 = 1,
+	CXIDV_CASSINI_1_1 = 2,
+	CXIDV_CASSINI_2_0 = 4,
+};
+
+enum cxidv_system_type_identifier {
+	CXIDV_SYSTEM_TYPE_CASSINI_1_ONLY = 0,
+	CXIDV_SYSTEM_TYPE_CASSINI_2_ONLY = 1,
+	CXIDV_SYSTEM_TYPE_MIXED = 2,
+};
+
+/*
+ * Device-wide HW properties. Field layout is this header's own stable ABI,
+ * not a copy of the kernel's internal cxi_ibv_devinfo layout, so the two can
+ * evolve independently.
+ */
+struct cxidv_devinfo {
+	uint32_t nid; /* 20-bit NIC address (NID) of this port */
+	uint32_t pid_bits; /* width of the PID field (6-9 bits) */
+	uint32_t pid_count; /* number of PIDs per VNI */
+	uint32_t pid_granule; /* PID space granularity */
+	uint32_t min_free_shift;
+	uint32_t rdzv_get_idx;
+	uint32_t vendor_id;
+	uint32_t device_id;
+	uint32_t device_rev;
+	uint32_t device_proto;
+	uint32_t device_platform;
+	uint32_t pct_eq;
+	int32_t uc_nic;
+	uint64_t link_mtu;
+	uint64_t link_speed;
+	uint8_t link_state;
+	uint16_t num_ptes;
+	uint16_t num_txqs;
+	uint16_t num_tgqs;
+	uint16_t num_eqs;
+	uint16_t num_cts;
+	uint16_t num_acs;
+	uint16_t num_tles;
+	uint16_t num_les;
+	uint32_t cassini_version; /* enum cxidv_cassini_version */
+	uint32_t system_type_identifier; /* enum cxidv_system_type_identifier */
+	char fru_description[16];
+};
+
+/*
+ * Returns 0 and fills @attr on success. Returns EOPNOTSUPP if @ibvctx is not
+ * a CXI device, or if the driver couldn't fetch this data at context-open
+ * time (see cxi_alloc_context() in cxi.c).
+ */
+int cxidv_query_device(struct ibv_context *ibvctx, struct cxidv_devinfo *attr);
+
+struct cxidv_mr_info {
+	uint64_t va;
+	uint64_t iova;
+	uint64_t length;
+	int32_t page_shift;
+	int32_t huge_shift;
+	uint32_t id;
+	uint32_t lac;
+};
+
+int cxidv_mr_from_ibv_mr(struct ibv_mr *mr, struct cxidv_mr_info *info);
+struct ibv_mr *cxidv_reg_native_mr(struct ibv_pd *pd, void *address, size_t length, uint32_t flags);
+
+/*
+ * Direct access to the CXI EQ backing an ibv_cq, for a consumer (libcxi)
+ * that needs to poll the hardware ring directly rather than through
+ * ibv_poll_cq(). ibv_create_cq()/ibv_destroy_cq() still own the CQ's
+ * lifetime; this just exposes what the provider already mmap'd for its own
+ * internal use (mirrors the mlx5dv_init_obj()/efadv_create_cq() pattern).
+ */
+struct cxidv_cq {
+	uint64_t comp_mask;
+	void *eq_buf; /* mmap'd event-ring buffer */
+	uint64_t eq_buf_size;
+	void *eq_db; /* mmap'd EQ doorbell/CSR */
+	uint64_t eq_db_size;
+	uint32_t eqn; /* hardware EQ index */
+};
+
+/*
+ * Returns 0 and fills @attr on success. Returns EOPNOTSUPP if @ibvcq was not
+ * created against a CXI device.
+ */
+int cxidv_cq_from_ibv_cq(struct ibv_cq *ibvcq, struct cxidv_cq *attr);
+
+/*
+ * Direct access to the TXQ/TGQ/PTE state backing an ibv_qp, for a consumer
+ * (libcxi) that needs to post commands directly onto the hardware rings
+ * rather than through ibv_post_send()/ibv_post_recv(). ibv_create_qp_ex()/
+ * ibv_destroy_qp() still own the QP's lifetime; this just exposes what the
+ * provider already mmap'd for its own internal use.
+ *
+ * pte_index is only valid once the QP has reached RTR (modify_qp); -1
+ * otherwise, mirroring struct cxi_qp's own convention.
+ */
+struct cxidv_qp {
+	uint64_t comp_mask;
+	void *txq_cmds;
+	uint64_t txq_cmds_size;
+	void *txq_db;
+	uint64_t txq_db_size;
+	uint32_t txq_idx;
+	uint32_t lcid;
+	void *tgq_cmds;
+	uint64_t tgq_cmds_size;
+	void *tgq_db;
+	uint64_t tgq_db_size;
+	uint32_t tgq_idx;
+	int32_t pte_index;
+};
+
+/*
+ * Returns 0 and fills @attr on success. Returns EOPNOTSUPP if @ibvqp was not
+ * created against a CXI device.
+ */
+int cxidv_qp_from_ibv_qp(struct ibv_qp *ibvqp, struct cxidv_qp *attr);
+
+/*
+ * Change the src_id (see IBV_RU_ATTR_SRC_ID) @ibvqp reports to its peers.
+ * Takes effect on the next work request posted; anything already built
+ * (posted or staged via the ibv_qp_ex builder but not yet flushed) keeps
+ * whatever value was in effect when it was built. Returns EOPNOTSUPP if
+ * @ibvqp was not created against a CXI device.
+ */
+int cxidv_modify_qp_src_id(struct ibv_qp *ibvqp, uint32_t src_id);
+
+enum cxidv_job_tc_flags {
+	CXIDV_JOB_TC_F_CREATE = 1U << 0,
+};
+
+struct cxidv_limits {
+	uint16_t max;
+	uint16_t res;
+};
+
+struct cxidv_job_tc_attr {
+	uint32_t flags;
+	uint32_t job_id;
+	uint32_t svc_id; /* existing service to bind, 0 = allocate one */
+	uint32_t tc;
+	uint32_t tc_type;
+	struct cxidv_limits ptes;
+	struct cxidv_limits txqs;
+	struct cxidv_limits tgqs;
+	struct cxidv_limits eqs;
+	struct cxidv_limits cts;
+	struct cxidv_limits les;
+	struct cxidv_limits tles;
+	struct cxidv_limits acs;
+	uint32_t bound_svc_id;
+};
+
+int cxidv_bind_job_tc(struct ibv_context *ibvctx, struct cxidv_job_tc_attr *attr);
+int cxidv_clear_job_tc(struct ibv_context *ibvctx, uint32_t tc, uint32_t tc_type);
+
+/*
+ * Select the traffic class subsequent QPs on @ibvctx are created with, without
+ * provisioning anything. Use this to run on an already-configured TC;
+ * cxidv_bind_job_tc() is only needed to create a TC or a JobID service.
+ *
+ * Cached updates from this function and cxidv_bind_job_tc() are synchronized
+ * with concurrent QP creation. Each QP uses the cached traffic class observed
+ * when the provider snapshots it during creation; a concurrent update may
+ * therefore affect that QP or a later one.
+ */
+int cxidv_set_default_tc(struct ibv_context *ibvctx, uint32_t tc);
+
+struct cxidv_tc_entry {
+	uint32_t tc;
+	uint32_t tc_type;
+	uint32_t res_req_dscp;
+	uint32_t unres_req_dscp;
+	uint32_t res_rsp_dscp;
+	uint32_t unres_rsp_dscp;
+	uint32_t req_pcp;
+	uint32_t rsp_pcp;
+	uint32_t ocuset;
+	uint32_t cq_tc;
+	uint32_t req_bc;
+	uint32_t flags;
+};
+
+#define CXIDV_TC_ENTRY_F_CREATED_BY_RDMA (1U << 0)
+
+int cxidv_query_tcs(struct ibv_context *ibvctx, struct cxidv_tc_entry *entries,
+		    uint32_t max_entries, uint32_t *count);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CXIDV_H__ */
diff --git a/providers/cxi/cxidv_telem.h b/providers/cxi/cxidv_telem.h
new file mode 100644
index 000000000000..6f8ff76d134b
--- /dev/null
+++ b/providers/cxi/cxidv_telem.h
@@ -0,0 +1,1984 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+/*
+ * Cassini telemetry items. The kernel knows items only by number;
+ * everything here is the user space naming of them.
+ *
+ * Read items through an ibv_counters object created with
+ * ibv_create_counters() and read with ibv_read_counters_ex(), which
+ * returns one value and one CLOCK_REALTIME timestamp in nanoseconds
+ * for each requested item. Items that do not exist on the device
+ * read as zero with a zero timestamp.
+ */
+
+#ifndef CXIDV_TELEM_H
+#define CXIDV_TELEM_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum cxidv_telem_item {
+	CXIDV_TELEM_UNDEFINED = 0,
+	CXIDV_TELEM_ATU_AT_STALL_CCP = 1,
+	CXIDV_TELEM_ATU_AT_STALL_NO_PTID = 2,
+	CXIDV_TELEM_ATU_AT_STALL_NP_CDTS = 3,
+	CXIDV_TELEM_ATU_AT_STALL_TARB_ARB = 4,
+	CXIDV_TELEM_ATU_ATS_DYNAMIC_STATE_CHANGE_CNTR = 5,
+	CXIDV_TELEM_ATU_ATS_INVAL_CNTR = 6,
+	CXIDV_TELEM_ATU_ATS_PRS_ODP_LATENCY_0 = 7,
+	CXIDV_TELEM_ATU_ATS_PRS_ODP_LATENCY_1 = 8,
+	CXIDV_TELEM_ATU_ATS_PRS_ODP_LATENCY_2 = 9,
+	CXIDV_TELEM_ATU_ATS_PRS_ODP_LATENCY_3 = 10,
+	CXIDV_TELEM_ATU_ATS_TRANS_ERR = 11,
+	CXIDV_TELEM_ATU_ATS_TRANS_LATENCY_0 = 12,
+	CXIDV_TELEM_ATU_ATS_TRANS_LATENCY_1 = 13,
+	CXIDV_TELEM_ATU_ATS_TRANS_LATENCY_2 = 14,
+	CXIDV_TELEM_ATU_ATS_TRANS_LATENCY_3 = 15,
+	CXIDV_TELEM_ATU_ATUCQ_INVAL_CNTR = 16,
+	CXIDV_TELEM_ATU_CACHE_EVICTIONS = 17,
+	CXIDV_TELEM_ATU_CACHE_HIT_BASE_PAGE_SIZE_0 = 18,
+	CXIDV_TELEM_ATU_CACHE_HIT_BASE_PAGE_SIZE_1 = 19,
+	CXIDV_TELEM_ATU_CACHE_HIT_BASE_PAGE_SIZE_2 = 20,
+	CXIDV_TELEM_ATU_CACHE_HIT_BASE_PAGE_SIZE_3 = 21,
+	CXIDV_TELEM_ATU_CACHE_HIT_DERIVATIVE1_PAGE_SIZE_0 = 22,
+	CXIDV_TELEM_ATU_CACHE_HIT_DERIVATIVE1_PAGE_SIZE_1 = 23,
+	CXIDV_TELEM_ATU_CACHE_HIT_DERIVATIVE1_PAGE_SIZE_2 = 24,
+	CXIDV_TELEM_ATU_CACHE_HIT_DERIVATIVE1_PAGE_SIZE_3 = 25,
+	CXIDV_TELEM_ATU_CACHE_HIT_DERIVATIVE2_PAGE_SIZE_0 = 26,
+	CXIDV_TELEM_ATU_CACHE_HIT_DERIVATIVE2_PAGE_SIZE_1 = 27,
+	CXIDV_TELEM_ATU_CACHE_HIT_DERIVATIVE2_PAGE_SIZE_2 = 28,
+	CXIDV_TELEM_ATU_CACHE_HIT_DERIVATIVE2_PAGE_SIZE_3 = 29,
+	CXIDV_TELEM_ATU_CACHE_MISS_0 = 30,
+	CXIDV_TELEM_ATU_CACHE_MISS_1 = 31,
+	CXIDV_TELEM_ATU_CACHE_MISS_2 = 32,
+	CXIDV_TELEM_ATU_CACHE_MISS_3 = 33,
+	CXIDV_TELEM_ATU_CACHE_MISS_EE = 34,
+	CXIDV_TELEM_ATU_CACHE_MISS_IXE = 35,
+	CXIDV_TELEM_ATU_CACHE_MISS_OXE = 36,
+	CXIDV_TELEM_ATU_CLIENT_REQ_EE = 37,
+	CXIDV_TELEM_ATU_CLIENT_REQ_IXE = 38,
+	CXIDV_TELEM_ATU_CLIENT_REQ_OXE = 39,
+	CXIDV_TELEM_ATU_CLIENT_RSP_NOT_OK_0 = 40,
+	CXIDV_TELEM_ATU_CLIENT_RSP_NOT_OK_1 = 41,
+	CXIDV_TELEM_ATU_CLIENT_RSP_NOT_OK_2 = 42,
+	CXIDV_TELEM_ATU_CLIENT_RSP_NOT_OK_3 = 43,
+	CXIDV_TELEM_ATU_FILTERED_REQUESTS = 44,
+	CXIDV_TELEM_ATU_IMPLICIT_ATS_EN_INVAL_CNTR = 45,
+	CXIDV_TELEM_ATU_IMPLICIT_FLR_INVAL_CNTR = 46,
+	CXIDV_TELEM_ATU_INVAL_STALL_ARB = 47,
+	CXIDV_TELEM_ATU_INVAL_STALL_CMPL_WAIT = 48,
+	CXIDV_TELEM_ATU_MEM_COR_ERR_CNTR = 49,
+	CXIDV_TELEM_ATU_MEM_UCOR_ERR_CNTR = 50,
+	CXIDV_TELEM_ATU_NIC_PRI_ODP_LATENCY_0 = 51,
+	CXIDV_TELEM_ATU_NIC_PRI_ODP_LATENCY_1 = 52,
+	CXIDV_TELEM_ATU_NIC_PRI_ODP_LATENCY_2 = 53,
+	CXIDV_TELEM_ATU_NIC_PRI_ODP_LATENCY_3 = 54,
+	CXIDV_TELEM_ATU_NTA_TRANS_LATENCY_0 = 55,
+	CXIDV_TELEM_ATU_NTA_TRANS_LATENCY_1 = 56,
+	CXIDV_TELEM_ATU_NTA_TRANS_LATENCY_2 = 57,
+	CXIDV_TELEM_ATU_NTA_TRANS_LATENCY_3 = 58,
+	CXIDV_TELEM_ATU_ODP_REQUESTS_0 = 59,
+	CXIDV_TELEM_ATU_ODP_REQUESTS_1 = 60,
+	CXIDV_TELEM_ATU_ODP_REQUESTS_2 = 61,
+	CXIDV_TELEM_ATU_ODP_REQUESTS_3 = 62,
+	CXIDV_TELEM_ATU_PCIE_ERR_POISONED = 63,
+	CXIDV_TELEM_ATU_PCIE_UNSUCCESS_CMPL = 64,
+	CXIDV_TELEM_CQ_CFG_EVENT_CNTS_OVF_CNT = 65,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_0 = 66,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_1 = 67,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_2 = 68,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_3 = 69,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_4 = 70,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_5 = 71,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_6 = 72,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_7 = 73,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_8 = 74,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_9 = 75,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_10 = 76,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_11 = 77,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_12 = 78,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_13 = 79,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_14 = 80,
+	CXIDV_TELEM_CQ_CQ_CMD_COUNTS_15 = 81,
+	CXIDV_TELEM_CQ_CQ_OXE_NUM_FLITS = 82,
+	CXIDV_TELEM_CQ_CQ_OXE_NUM_IDLES = 83,
+	CXIDV_TELEM_CQ_CQ_OXE_NUM_STALLS = 84,
+	CXIDV_TELEM_CQ_CQ_TOU_NUM_FLITS = 85,
+	CXIDV_TELEM_CQ_CQ_TOU_NUM_IDLES = 86,
+	CXIDV_TELEM_CQ_CQ_TOU_NUM_STALLS = 87,
+	CXIDV_TELEM_CQ_CYCLES_BLOCKED_0 = 88,
+	CXIDV_TELEM_CQ_CYCLES_BLOCKED_1 = 89,
+	CXIDV_TELEM_CQ_CYCLES_BLOCKED_2 = 90,
+	CXIDV_TELEM_CQ_CYCLES_BLOCKED_3 = 91,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_0 = 92,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_1 = 93,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_2 = 94,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_3 = 95,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_4 = 96,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_5 = 97,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_6 = 98,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_7 = 99,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_8 = 100,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_9 = 101,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_10 = 102,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_11 = 103,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_12 = 104,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_13 = 105,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_14 = 106,
+	CXIDV_TELEM_CQ_DMA_CMD_COUNTS_15 = 107,
+	CXIDV_TELEM_CQ_FAIL_TGT_CNTR = 108,
+	CXIDV_TELEM_CQ_FAIL_TX_CNTR = 109,
+	CXIDV_TELEM_CQ_MEM_COR_ERR_CNTR = 110,
+	CXIDV_TELEM_CQ_MEM_UCOR_ERR_CNTR = 111,
+	CXIDV_TELEM_CQ_NUM_CQ_CMDS_0 = 112,
+	CXIDV_TELEM_CQ_NUM_CQ_CMDS_1 = 113,
+	CXIDV_TELEM_CQ_NUM_CQ_CMDS_2 = 114,
+	CXIDV_TELEM_CQ_NUM_CQ_CMDS_3 = 115,
+	CXIDV_TELEM_CQ_NUM_DMA_CMDS_0 = 116,
+	CXIDV_TELEM_CQ_NUM_DMA_CMDS_1 = 117,
+	CXIDV_TELEM_CQ_NUM_DMA_CMDS_2 = 118,
+	CXIDV_TELEM_CQ_NUM_DMA_CMDS_3 = 119,
+	CXIDV_TELEM_CQ_NUM_IDC_CMDS_0 = 120,
+	CXIDV_TELEM_CQ_NUM_IDC_CMDS_1 = 121,
+	CXIDV_TELEM_CQ_NUM_IDC_CMDS_2 = 122,
+	CXIDV_TELEM_CQ_NUM_IDC_CMDS_3 = 123,
+	CXIDV_TELEM_CQ_NUM_LL_CMDS_0 = 124,
+	CXIDV_TELEM_CQ_NUM_LL_CMDS_1 = 125,
+	CXIDV_TELEM_CQ_NUM_LL_CMDS_2 = 126,
+	CXIDV_TELEM_CQ_NUM_LL_CMDS_3 = 127,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_RECEIVED_0 = 128,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_RECEIVED_1 = 129,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_RECEIVED_2 = 130,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_RECEIVED_3 = 131,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_REJECTED_0 = 132,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_REJECTED_1 = 133,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_REJECTED_2 = 134,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_REJECTED_3 = 135,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_SPLIT_0 = 136,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_SPLIT_1 = 137,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_SPLIT_2 = 138,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_SPLIT_3 = 139,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_SUCCESSFUL_0 = 140,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_SUCCESSFUL_1 = 141,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_SUCCESSFUL_2 = 142,
+	CXIDV_TELEM_CQ_NUM_LL_OPS_SUCCESSFUL_3 = 143,
+	CXIDV_TELEM_CQ_NUM_TGQ_CMD_READS_0 = 144,
+	CXIDV_TELEM_CQ_NUM_TGQ_CMD_READS_1 = 145,
+	CXIDV_TELEM_CQ_NUM_TGQ_CMD_READS_2 = 146,
+	CXIDV_TELEM_CQ_NUM_TGQ_CMD_READS_3 = 147,
+	CXIDV_TELEM_CQ_NUM_TGT_CMD_ARG_ERRORS = 148,
+	CXIDV_TELEM_CQ_NUM_TGT_CMD_PERM_ERRORS = 149,
+	CXIDV_TELEM_CQ_NUM_TGT_CMDS_0 = 150,
+	CXIDV_TELEM_CQ_NUM_TGT_CMDS_1 = 151,
+	CXIDV_TELEM_CQ_NUM_TGT_CMDS_2 = 152,
+	CXIDV_TELEM_CQ_NUM_TGT_CMDS_3 = 153,
+	CXIDV_TELEM_CQ_NUM_TOU_CMD_READS_0 = 154,
+	CXIDV_TELEM_CQ_NUM_TOU_CMD_READS_1 = 155,
+	CXIDV_TELEM_CQ_NUM_TOU_CMD_READS_2 = 156,
+	CXIDV_TELEM_CQ_NUM_TOU_CMD_READS_3 = 157,
+	CXIDV_TELEM_CQ_NUM_TX_CMD_ALIGN_ERRORS = 158,
+	CXIDV_TELEM_CQ_NUM_TX_CMD_ARG_ERRORS = 159,
+	CXIDV_TELEM_CQ_NUM_TX_CMD_OP_ERRORS = 160,
+	CXIDV_TELEM_CQ_NUM_TX_CMD_PERM_ERRORS = 161,
+	CXIDV_TELEM_CQ_NUM_TXQ_CMD_READS_0 = 162,
+	CXIDV_TELEM_CQ_NUM_TXQ_CMD_READS_1 = 163,
+	CXIDV_TELEM_CQ_NUM_TXQ_CMD_READS_2 = 164,
+	CXIDV_TELEM_CQ_NUM_TXQ_CMD_READS_3 = 165,
+	CXIDV_TELEM_CQ_RARB_ERR_CNTR = 166,
+	CXIDV_TELEM_CQ_RARB_LL_ERR_CNTR = 167,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_EE_EVENT_CREDITS = 168,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_FQ_SH_CREDITS = 169,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_FQ_TOT_CREDITS = 170,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_LPE_CMD_CREDITS = 171,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_LPE_RCV_FIFO_CREDITS = 172,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_PREFETCH_TOU_CREDITS = 173,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_TARB_NP_CREDITS = 174,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_TARB_P_CREDITS = 175,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_TGQ_CMD_FAIL_EVENT_CREDITS = 176,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_TOU_CMD_FAIL_EVENT_CREDITS = 177,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_TOU_EVENT_CREDITS = 178,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_TOU_FQ_CREDITS = 179,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_TOU_WB_CREDITS = 180,
+	CXIDV_TELEM_CQ_STS_CREDITS_IN_USE_TXQ_CMD_FAIL_EVENT_CREDITS = 181,
+	CXIDV_TELEM_CQ_STS_DMA_PAYLOAD_DATA_0 = 182,
+	CXIDV_TELEM_CQ_STS_DMA_PAYLOAD_DATA_1 = 183,
+	CXIDV_TELEM_CQ_STS_DMA_PAYLOAD_DATA_2 = 184,
+	CXIDV_TELEM_CQ_STS_DMA_PAYLOAD_DATA_3 = 185,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_0 = 186,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_1 = 187,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_2 = 188,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_3 = 189,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_4 = 190,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_5 = 191,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_6 = 192,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_7 = 193,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_8 = 194,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_9 = 195,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_10 = 196,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_11 = 197,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_12 = 198,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_13 = 199,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_14 = 200,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_15 = 201,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_16 = 202,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_17 = 203,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_18 = 204,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_19 = 205,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_20 = 206,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_21 = 207,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_22 = 208,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_23 = 209,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_24 = 210,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_25 = 211,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_26 = 212,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_27 = 213,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_28 = 214,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_29 = 215,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_30 = 216,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_31 = 217,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_32 = 218,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_33 = 219,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_34 = 220,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_35 = 221,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_36 = 222,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_37 = 223,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_38 = 224,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_39 = 225,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_40 = 226,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_41 = 227,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_42 = 228,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_43 = 229,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_44 = 230,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_45 = 231,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_46 = 232,
+	CXIDV_TELEM_CQ_STS_FQ_LOAD_47 = 233,
+	CXIDV_TELEM_CQ_STS_IDC_PAYLOAD_DATA_0 = 234,
+	CXIDV_TELEM_CQ_STS_IDC_PAYLOAD_DATA_1 = 235,
+	CXIDV_TELEM_CQ_STS_IDC_PAYLOAD_DATA_2 = 236,
+	CXIDV_TELEM_CQ_STS_IDC_PAYLOAD_DATA_3 = 237,
+	CXIDV_TELEM_CQ_STS_LL_DMA_PAYLOAD_DATA_0 = 238,
+	CXIDV_TELEM_CQ_STS_LL_DMA_PAYLOAD_DATA_1 = 239,
+	CXIDV_TELEM_CQ_STS_LL_DMA_PAYLOAD_DATA_2 = 240,
+	CXIDV_TELEM_CQ_STS_LL_DMA_PAYLOAD_DATA_3 = 241,
+	CXIDV_TELEM_CQ_STS_LL_IDC_PAYLOAD_DATA_0 = 242,
+	CXIDV_TELEM_CQ_STS_LL_IDC_PAYLOAD_DATA_1 = 243,
+	CXIDV_TELEM_CQ_STS_LL_IDC_PAYLOAD_DATA_2 = 244,
+	CXIDV_TELEM_CQ_STS_LL_IDC_PAYLOAD_DATA_3 = 245,
+	CXIDV_TELEM_CQ_STS_TLE_IN_USE_0 = 246,
+	CXIDV_TELEM_CQ_STS_TLE_IN_USE_1 = 247,
+	CXIDV_TELEM_CQ_STS_TLE_IN_USE_2 = 248,
+	CXIDV_TELEM_CQ_STS_TLE_IN_USE_3 = 249,
+	CXIDV_TELEM_CQ_STS_TOU_PAYLOAD_DATA_0 = 250,
+	CXIDV_TELEM_CQ_STS_TOU_PAYLOAD_DATA_1 = 251,
+	CXIDV_TELEM_CQ_STS_TOU_PAYLOAD_DATA_2 = 252,
+	CXIDV_TELEM_CQ_STS_TOU_PAYLOAD_DATA_3 = 253,
+	CXIDV_TELEM_CQ_SUCCESS_TGT_CNTR = 254,
+	CXIDV_TELEM_CQ_SUCCESS_TX_CNTR = 255,
+	CXIDV_TELEM_CQ_TGT_WAITING_ON_READ_0 = 256,
+	CXIDV_TELEM_CQ_TGT_WAITING_ON_READ_1 = 257,
+	CXIDV_TELEM_CQ_TGT_WAITING_ON_READ_2 = 258,
+	CXIDV_TELEM_CQ_TGT_WAITING_ON_READ_3 = 259,
+	CXIDV_TELEM_CQ_TX_WAITING_ON_READ_0 = 260,
+	CXIDV_TELEM_CQ_TX_WAITING_ON_READ_1 = 261,
+	CXIDV_TELEM_CQ_TX_WAITING_ON_READ_2 = 262,
+	CXIDV_TELEM_CQ_TX_WAITING_ON_READ_3 = 263,
+	CXIDV_TELEM_CQ_WR_PTR_UPDT_ERR_CNTR = 264,
+	CXIDV_TELEM_EE_ADDR_TRANS_PREFETCH_CNTR_0 = 265,
+	CXIDV_TELEM_EE_ADDR_TRANS_PREFETCH_CNTR_1 = 266,
+	CXIDV_TELEM_EE_ADDR_TRANS_PREFETCH_CNTR_2 = 267,
+	CXIDV_TELEM_EE_ADDR_TRANS_PREFETCH_CNTR_3 = 268,
+	CXIDV_TELEM_EE_ADDR_TRANS_REQ_CNTR = 269,
+	CXIDV_TELEM_EE_CBS_WRITTEN_CNTR_0 = 270,
+	CXIDV_TELEM_EE_CBS_WRITTEN_CNTR_1 = 271,
+	CXIDV_TELEM_EE_CBS_WRITTEN_CNTR_2 = 272,
+	CXIDV_TELEM_EE_CBS_WRITTEN_CNTR_3 = 273,
+	CXIDV_TELEM_EE_CE_ARB_OUT_EVENT_CNTR = 274,
+	CXIDV_TELEM_EE_CE_ARB_OUT_STALL_CNTR = 275,
+	CXIDV_TELEM_EE_CQ_EVENT_REQ_CNTR = 276,
+	CXIDV_TELEM_EE_CQ_FE_CNTR = 277,
+	CXIDV_TELEM_EE_CQ_FE_STALL_CNTR = 278,
+	CXIDV_TELEM_EE_DEFERRED_EQ_SWITCH_CNTR_0 = 279,
+	CXIDV_TELEM_EE_DEFERRED_EQ_SWITCH_CNTR_1 = 280,
+	CXIDV_TELEM_EE_DEFERRED_EQ_SWITCH_CNTR_2 = 281,
+	CXIDV_TELEM_EE_DEFERRED_EQ_SWITCH_CNTR_3 = 282,
+	CXIDV_TELEM_EE_EQ_BUFFER_SWITCH_CNTR_0 = 283,
+	CXIDV_TELEM_EE_EQ_BUFFER_SWITCH_CNTR_1 = 284,
+	CXIDV_TELEM_EE_EQ_BUFFER_SWITCH_CNTR_2 = 285,
+	CXIDV_TELEM_EE_EQ_BUFFER_SWITCH_CNTR_3 = 286,
+	CXIDV_TELEM_EE_EQ_DSABLD_EVENT_ERR_CNTR = 287,
+	CXIDV_TELEM_EE_EQ_DSABLD_LPEQ_ERR_CNTR = 288,
+	CXIDV_TELEM_EE_EQ_DSABLD_SWS_ERR_CNTR = 289,
+	CXIDV_TELEM_EE_EQ_RSRVN_UFLW_ERR_CNTR = 290,
+	CXIDV_TELEM_EE_EQ_STATE_UCOR_ERR_CNTR = 291,
+	CXIDV_TELEM_EE_EQ_STATUS_UPDATE_CNTR_0 = 292,
+	CXIDV_TELEM_EE_EQ_STATUS_UPDATE_CNTR_1 = 293,
+	CXIDV_TELEM_EE_EQ_STATUS_UPDATE_CNTR_2 = 294,
+	CXIDV_TELEM_EE_EQ_STATUS_UPDATE_CNTR_3 = 295,
+	CXIDV_TELEM_EE_EQ_SW_STATE_WR_CNTR_0 = 296,
+	CXIDV_TELEM_EE_EQ_SW_STATE_WR_CNTR_1 = 297,
+	CXIDV_TELEM_EE_EQ_SW_STATE_WR_CNTR_2 = 298,
+	CXIDV_TELEM_EE_EQ_SW_STATE_WR_CNTR_3 = 299,
+	CXIDV_TELEM_EE_EQS_ARB_OUT_REQ_CNTR = 300,
+	CXIDV_TELEM_EE_EQS_CSR_REQ_CNTR = 301,
+	CXIDV_TELEM_EE_EQS_CSR_STALL_CNTR = 302,
+	CXIDV_TELEM_EE_EQS_EVENT_REQ_CNTR = 303,
+	CXIDV_TELEM_EE_EQS_EVENT_STALL_CNTR = 304,
+	CXIDV_TELEM_EE_EQS_EXPIRED_CB_REQ_CNTR = 305,
+	CXIDV_TELEM_EE_EQS_EXPIRED_CB_STALL_CNTR = 306,
+	CXIDV_TELEM_EE_EQS_FREE_CB_STALL_CNTR = 307,
+	CXIDV_TELEM_EE_EQS_HWS_INIT_REQ_CNTR = 308,
+	CXIDV_TELEM_EE_EQS_HWS_INIT_STALL_CNTR = 309,
+	CXIDV_TELEM_EE_EQS_LPE_QUERY_REQ_CNTR = 310,
+	CXIDV_TELEM_EE_EQS_STS_UPDT_REQ_CNTR = 311,
+	CXIDV_TELEM_EE_EQS_STS_UPDT_STALL_CNTR = 312,
+	CXIDV_TELEM_EE_EQS_SWS_WR_REQ_CNTR = 313,
+	CXIDV_TELEM_EE_EQS_SWS_WR_STALL_CNTR = 314,
+	CXIDV_TELEM_EE_EVENT_ACK_CNTR = 315,
+	CXIDV_TELEM_EE_EVENT_ATOMIC_CNTR = 316,
+	CXIDV_TELEM_EE_EVENT_ATOMIC_OVERFLOW_CNTR = 317,
+	CXIDV_TELEM_EE_EVENT_COMMAND_FAILURE_CNTR = 318,
+	CXIDV_TELEM_EE_EVENT_EQ_SWITCH_CNTR = 319,
+	CXIDV_TELEM_EE_EVENT_ERROR_CNTR = 320,
+	CXIDV_TELEM_EE_EVENT_ETHERNET_CNTR = 321,
+	CXIDV_TELEM_EE_EVENT_ETHERNET_FGFC_CNTR = 322,
+	CXIDV_TELEM_EE_EVENT_FETCH_ATOMIC_CNTR = 323,
+	CXIDV_TELEM_EE_EVENT_FETCH_ATOMIC_OVERFLOW_CNTR = 324,
+	CXIDV_TELEM_EE_EVENT_GET_CNTR = 325,
+	CXIDV_TELEM_EE_EVENT_GET_OVERFLOW_CNTR = 326,
+	CXIDV_TELEM_EE_EVENT_LINK_CNTR = 327,
+	CXIDV_TELEM_EE_EVENT_MATCH_CNTR = 328,
+	CXIDV_TELEM_EE_EVENT_NULL_EVENT_CNTR = 329,
+	CXIDV_TELEM_EE_EVENT_PCT_CNTR = 330,
+	CXIDV_TELEM_EE_EVENT_PUT_CNTR = 331,
+	CXIDV_TELEM_EE_EVENT_PUT_OVERFLOW_CNTR = 332,
+	CXIDV_TELEM_EE_EVENT_RENDEZVOUS_CNTR = 333,
+	CXIDV_TELEM_EE_EVENT_REPLY_CNTR = 334,
+	CXIDV_TELEM_EE_EVENT_SEARCH_CNTR = 335,
+	CXIDV_TELEM_EE_EVENT_SEND_CNTR = 336,
+	CXIDV_TELEM_EE_EVENT_STATE_CHANGE_CNTR = 337,
+	CXIDV_TELEM_EE_EVENT_TIMESTAMP_CNTR = 338,
+	CXIDV_TELEM_EE_EVENT_TRIGGERED_OP_CNTR = 339,
+	CXIDV_TELEM_EE_EVENT_UNLINK_CNTR = 340,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_FC_SC_CNTR_0 = 341,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_FC_SC_CNTR_1 = 342,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_FC_SC_CNTR_2 = 343,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_FC_SC_CNTR_3 = 344,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_ORDINARY_CNTR_0 = 345,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_ORDINARY_CNTR_1 = 346,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_ORDINARY_CNTR_2 = 347,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_ORDINARY_CNTR_3 = 348,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_RSRVN_CNTR_0 = 349,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_RSRVN_CNTR_1 = 350,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_RSRVN_CNTR_2 = 351,
+	CXIDV_TELEM_EE_EVENTS_DROPPED_RSRVN_CNTR_3 = 352,
+	CXIDV_TELEM_EE_EVENTS_ENQUEUED_CNTR_0 = 353,
+	CXIDV_TELEM_EE_EVENTS_ENQUEUED_CNTR_1 = 354,
+	CXIDV_TELEM_EE_EVENTS_ENQUEUED_CNTR_2 = 355,
+	CXIDV_TELEM_EE_EVENTS_ENQUEUED_CNTR_3 = 356,
+	CXIDV_TELEM_EE_EXPIRED_CBS_WRITTEN_CNTR_0 = 357,
+	CXIDV_TELEM_EE_EXPIRED_CBS_WRITTEN_CNTR_1 = 358,
+	CXIDV_TELEM_EE_EXPIRED_CBS_WRITTEN_CNTR_2 = 359,
+	CXIDV_TELEM_EE_EXPIRED_CBS_WRITTEN_CNTR_3 = 360,
+	CXIDV_TELEM_EE_FE_ARB_OUT_EVENT_CNTR = 361,
+	CXIDV_TELEM_EE_FE_ARB_OUT_STALL_CNTR = 362,
+	CXIDV_TELEM_EE_HNI_EVENT_REQ_CNTR = 363,
+	CXIDV_TELEM_EE_HNI_FE_CNTR = 364,
+	CXIDV_TELEM_EE_HNI_FE_STALL_CNTR = 365,
+	CXIDV_TELEM_EE_IXE_CE_CNTR = 366,
+	CXIDV_TELEM_EE_IXE_CE_STALL_CNTR = 367,
+	CXIDV_TELEM_EE_IXE_DD_CNTR = 368,
+	CXIDV_TELEM_EE_IXE_EVENT_REQ_CNTR = 369,
+	CXIDV_TELEM_EE_IXE_FE_CNTR = 370,
+	CXIDV_TELEM_EE_IXE_FE_STALL_CNTR = 371,
+	CXIDV_TELEM_EE_LPE_CE_CNTR = 372,
+	CXIDV_TELEM_EE_LPE_CE_STALL_CNTR = 373,
+	CXIDV_TELEM_EE_LPE_DD_CNTR = 374,
+	CXIDV_TELEM_EE_LPE_EVENT_REQ_CNTR = 375,
+	CXIDV_TELEM_EE_LPE_FE_CNTR = 376,
+	CXIDV_TELEM_EE_LPE_FE_STALL_CNTR = 377,
+	CXIDV_TELEM_EE_LPE_QUERY_EQ_NONE_CNTR = 378,
+	CXIDV_TELEM_EE_MEM_COR_ERR_CNTR = 379,
+	CXIDV_TELEM_EE_MEM_UCOR_ERR_CNTR = 380,
+	CXIDV_TELEM_EE_MST_CE_CNTR = 381,
+	CXIDV_TELEM_EE_MST_CE_STALL_CNTR = 382,
+	CXIDV_TELEM_EE_MST_DD_CNTR = 383,
+	CXIDV_TELEM_EE_MST_EVENT_REQ_CNTR = 384,
+	CXIDV_TELEM_EE_MST_FE_CNTR = 385,
+	CXIDV_TELEM_EE_MST_FE_STALL_CNTR = 386,
+	CXIDV_TELEM_EE_PARTIAL_CBS_WRITTEN_CNTR_0 = 387,
+	CXIDV_TELEM_EE_PARTIAL_CBS_WRITTEN_CNTR_1 = 388,
+	CXIDV_TELEM_EE_PARTIAL_CBS_WRITTEN_CNTR_2 = 389,
+	CXIDV_TELEM_EE_PARTIAL_CBS_WRITTEN_CNTR_3 = 390,
+	CXIDV_TELEM_EE_PCT_CE_CNTR = 391,
+	CXIDV_TELEM_EE_PCT_CE_STALL_CNTR = 392,
+	CXIDV_TELEM_EE_PCT_DD_CNTR = 393,
+	CXIDV_TELEM_EE_PCT_EVENT_REQ_CNTR = 394,
+	CXIDV_TELEM_EE_PCT_FE_CNTR = 395,
+	CXIDV_TELEM_EE_PCT_FE_STALL_CNTR = 396,
+	CXIDV_TELEM_EE_RARB_HW_ERR_CNTR = 397,
+	CXIDV_TELEM_EE_RARB_SW_ERR_CNTR = 398,
+	CXIDV_TELEM_EE_STS_ECBS_IN_USE_ECBS_IN_USE = 399,
+	CXIDV_TELEM_EE_STS_ECBS_IN_USE_MAX_ECBS_IN_USE = 400,
+	CXIDV_TELEM_EE_TARB_ERR_CNTR = 401,
+	CXIDV_TELEM_EE_TARB_IRQ_REQ_CNTR = 402,
+	CXIDV_TELEM_EE_TARB_STALL_CNTR = 403,
+	CXIDV_TELEM_EE_TARB_WR_REQ_CNTR = 404,
+	CXIDV_TELEM_EE_TS_FE_CNTR = 405,
+	CXIDV_TELEM_EE_TS_FE_STALL_CNTR = 406,
+	CXIDV_TELEM_EE_UNXPCTD_TRNSLTN_RSP_ERR_CNTR = 407,
+	CXIDV_TELEM_HNI_CFG_EVENT_CNTS_OVF_CNT = 408,
+	CXIDV_TELEM_HNI_COR_ECC_ERR_CNTR = 409,
+	CXIDV_TELEM_HNI_DISCARD_CNTR_0 = 410,
+	CXIDV_TELEM_HNI_DISCARD_CNTR_1 = 411,
+	CXIDV_TELEM_HNI_DISCARD_CNTR_2 = 412,
+	CXIDV_TELEM_HNI_DISCARD_CNTR_3 = 413,
+	CXIDV_TELEM_HNI_DISCARD_CNTR_4 = 414,
+	CXIDV_TELEM_HNI_DISCARD_CNTR_5 = 415,
+	CXIDV_TELEM_HNI_DISCARD_CNTR_6 = 416,
+	CXIDV_TELEM_HNI_DISCARD_CNTR_7 = 417,
+	CXIDV_TELEM_HNI_FGFC_DISCARD = 418,
+	CXIDV_TELEM_HNI_FGFC_EVENT_XOFF = 419,
+	CXIDV_TELEM_HNI_FGFC_EVENT_XON = 420,
+	CXIDV_TELEM_HNI_FGFC_IPV4 = 421,
+	CXIDV_TELEM_HNI_FGFC_IPV6 = 422,
+	CXIDV_TELEM_HNI_FGFC_L2 = 423,
+	CXIDV_TELEM_HNI_FGFC_MATCH = 424,
+	CXIDV_TELEM_HNI_FGFC_PORT = 425,
+	CXIDV_TELEM_HNI_HRP_ACK = 426,
+	CXIDV_TELEM_HNI_HRP_RESP = 427,
+	CXIDV_TELEM_HNI_LLR_RX_ACK_CTL_OS = 428,
+	CXIDV_TELEM_HNI_LLR_RX_ACK_NACK_ERROR = 429,
+	CXIDV_TELEM_HNI_LLR_RX_ACK_NACK_SEQ_ERR = 430,
+	CXIDV_TELEM_HNI_LLR_RX_BAD_CTL_FR = 431,
+	CXIDV_TELEM_HNI_LLR_RX_BAD_LOSSLESS = 432,
+	CXIDV_TELEM_HNI_LLR_RX_BAD_LOSSY = 433,
+	CXIDV_TELEM_HNI_LLR_RX_DUPLICATE_SEQ = 434,
+	CXIDV_TELEM_HNI_LLR_RX_EXPECTED_SEQ_BAD = 435,
+	CXIDV_TELEM_HNI_LLR_RX_EXPECTED_SEQ_GOOD = 436,
+	CXIDV_TELEM_HNI_LLR_RX_EXPECTED_SEQ_POISONED = 437,
+	CXIDV_TELEM_HNI_LLR_RX_INIT_CTL_OS = 438,
+	CXIDV_TELEM_HNI_LLR_RX_INIT_ECHO_CTL_OS = 439,
+	CXIDV_TELEM_HNI_LLR_RX_LOOP_TIME_REQ_CTL_FR = 440,
+	CXIDV_TELEM_HNI_LLR_RX_LOOP_TIME_RSP_CTL_FR = 441,
+	CXIDV_TELEM_HNI_LLR_RX_NACK_CTL_OS = 442,
+	CXIDV_TELEM_HNI_LLR_RX_OK_LOSSLESS = 443,
+	CXIDV_TELEM_HNI_LLR_RX_OK_LOSSY = 444,
+	CXIDV_TELEM_HNI_LLR_RX_POISONED_LOSSLESS = 445,
+	CXIDV_TELEM_HNI_LLR_RX_POISONED_LOSSY = 446,
+	CXIDV_TELEM_HNI_LLR_RX_REPLAY_EVENT = 447,
+	CXIDV_TELEM_HNI_LLR_RX_UNEXPECTED_SEQ = 448,
+	CXIDV_TELEM_HNI_LLR_TX_ACK_CTL_OS = 449,
+	CXIDV_TELEM_HNI_LLR_TX_BAD_LOSSLESS = 450,
+	CXIDV_TELEM_HNI_LLR_TX_BAD_LOSSLESS_RPT = 451,
+	CXIDV_TELEM_HNI_LLR_TX_BAD_LOSSY = 452,
+	CXIDV_TELEM_HNI_LLR_TX_DISCARD = 453,
+	CXIDV_TELEM_HNI_LLR_TX_INIT_CTL_OS = 454,
+	CXIDV_TELEM_HNI_LLR_TX_INIT_ECHO_CTL_OS = 455,
+	CXIDV_TELEM_HNI_LLR_TX_LLR_BLOCKED = 456,
+	CXIDV_TELEM_HNI_LLR_TX_LLR_UNBLOCKED = 457,
+	CXIDV_TELEM_HNI_LLR_TX_LOOP_TIME_REQ_CTL_FR = 458,
+	CXIDV_TELEM_HNI_LLR_TX_LOOP_TIME_RSP_CTL_FR = 459,
+	CXIDV_TELEM_HNI_LLR_TX_NACK_CTL_OS = 460,
+	CXIDV_TELEM_HNI_LLR_TX_OK_BYPASS = 461,
+	CXIDV_TELEM_HNI_LLR_TX_OK_LOSSLESS = 462,
+	CXIDV_TELEM_HNI_LLR_TX_OK_LOSSLESS_RPT = 463,
+	CXIDV_TELEM_HNI_LLR_TX_OK_LOSSY = 464,
+	CXIDV_TELEM_HNI_LLR_TX_POISONED_LOSSLESS = 465,
+	CXIDV_TELEM_HNI_LLR_TX_POISONED_LOSSLESS_RPT = 466,
+	CXIDV_TELEM_HNI_LLR_TX_POISONED_LOSSY = 467,
+	CXIDV_TELEM_HNI_LLR_TX_REPLAY_EVENT = 468,
+	CXIDV_TELEM_HNI_MAC_RX_FRAGMENT = 469,
+	CXIDV_TELEM_HNI_MAC_RX_ILLEGAL_SIZE = 470,
+	CXIDV_TELEM_HNI_MAC_RX_PREAMBLE_ERROR = 471,
+	CXIDV_TELEM_HNI_MAC_TX_IFG_ADJUSTMENT_SYNC = 472,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_RECV_BY_TC_0 = 473,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_RECV_BY_TC_1 = 474,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_RECV_BY_TC_2 = 475,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_RECV_BY_TC_3 = 476,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_RECV_BY_TC_4 = 477,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_RECV_BY_TC_5 = 478,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_RECV_BY_TC_6 = 479,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_RECV_BY_TC_7 = 480,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_SENT_BY_TC_0 = 481,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_SENT_BY_TC_1 = 482,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_SENT_BY_TC_2 = 483,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_SENT_BY_TC_3 = 484,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_SENT_BY_TC_4 = 485,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_SENT_BY_TC_5 = 486,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_SENT_BY_TC_6 = 487,
+	CXIDV_TELEM_HNI_MULTICAST_PKTS_SENT_BY_TC_7 = 488,
+	CXIDV_TELEM_HNI_PAUSE_RECV_0 = 489,
+	CXIDV_TELEM_HNI_PAUSE_RECV_1 = 490,
+	CXIDV_TELEM_HNI_PAUSE_RECV_2 = 491,
+	CXIDV_TELEM_HNI_PAUSE_RECV_3 = 492,
+	CXIDV_TELEM_HNI_PAUSE_RECV_4 = 493,
+	CXIDV_TELEM_HNI_PAUSE_RECV_5 = 494,
+	CXIDV_TELEM_HNI_PAUSE_RECV_6 = 495,
+	CXIDV_TELEM_HNI_PAUSE_RECV_7 = 496,
+	CXIDV_TELEM_HNI_PAUSE_REFRESH = 497,
+	CXIDV_TELEM_HNI_PAUSE_SENT = 498,
+	CXIDV_TELEM_HNI_PAUSE_XOFF_SENT_0 = 499,
+	CXIDV_TELEM_HNI_PAUSE_XOFF_SENT_1 = 500,
+	CXIDV_TELEM_HNI_PAUSE_XOFF_SENT_2 = 501,
+	CXIDV_TELEM_HNI_PAUSE_XOFF_SENT_3 = 502,
+	CXIDV_TELEM_HNI_PAUSE_XOFF_SENT_4 = 503,
+	CXIDV_TELEM_HNI_PAUSE_XOFF_SENT_5 = 504,
+	CXIDV_TELEM_HNI_PAUSE_XOFF_SENT_6 = 505,
+	CXIDV_TELEM_HNI_PAUSE_XOFF_SENT_7 = 506,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW = 507,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_0 = 508,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_1 = 509,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_2 = 510,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_3 = 511,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_4 = 512,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_5 = 513,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_6 = 514,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_7 = 515,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_8 = 516,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_9 = 517,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_10 = 518,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_11 = 519,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_12 = 520,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_13 = 521,
+	CXIDV_TELEM_HNI_PCS_CORRECTED_CW_BIN_14 = 522,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_0 = 523,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_1 = 524,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_2 = 525,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_3 = 526,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_4 = 527,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_5 = 528,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_6 = 529,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_7 = 530,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_8 = 531,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_9 = 532,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_10 = 533,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_11 = 534,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_12 = 535,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_13 = 536,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_14 = 537,
+	CXIDV_TELEM_HNI_PCS_FECL_ERRORS_15 = 538,
+	CXIDV_TELEM_HNI_PCS_GOOD_CW = 539,
+	CXIDV_TELEM_HNI_PCS_PML_MBE_ERROR_CNT = 540,
+	CXIDV_TELEM_HNI_PCS_PML_SBE_ERROR_CNT = 541,
+	CXIDV_TELEM_HNI_PCS_UNCORRECTED_CW = 542,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_0 = 543,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_1 = 544,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_2 = 545,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_3 = 546,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_4 = 547,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_5 = 548,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_6 = 549,
+	CXIDV_TELEM_HNI_PFC_FIFO_OFLW_CNTR_7 = 550,
+	CXIDV_TELEM_HNI_PKTS_RECV_BY_TC_0 = 551,
+	CXIDV_TELEM_HNI_PKTS_RECV_BY_TC_1 = 552,
+	CXIDV_TELEM_HNI_PKTS_RECV_BY_TC_2 = 553,
+	CXIDV_TELEM_HNI_PKTS_RECV_BY_TC_3 = 554,
+	CXIDV_TELEM_HNI_PKTS_RECV_BY_TC_4 = 555,
+	CXIDV_TELEM_HNI_PKTS_RECV_BY_TC_5 = 556,
+	CXIDV_TELEM_HNI_PKTS_RECV_BY_TC_6 = 557,
+	CXIDV_TELEM_HNI_PKTS_RECV_BY_TC_7 = 558,
+	CXIDV_TELEM_HNI_PKTS_SENT_BY_TC_0 = 559,
+	CXIDV_TELEM_HNI_PKTS_SENT_BY_TC_1 = 560,
+	CXIDV_TELEM_HNI_PKTS_SENT_BY_TC_2 = 561,
+	CXIDV_TELEM_HNI_PKTS_SENT_BY_TC_3 = 562,
+	CXIDV_TELEM_HNI_PKTS_SENT_BY_TC_4 = 563,
+	CXIDV_TELEM_HNI_PKTS_SENT_BY_TC_5 = 564,
+	CXIDV_TELEM_HNI_PKTS_SENT_BY_TC_6 = 565,
+	CXIDV_TELEM_HNI_PKTS_SENT_BY_TC_7 = 566,
+	CXIDV_TELEM_HNI_RX_BAD_IEEE = 567,
+	CXIDV_TELEM_HNI_RX_BAD_OPT = 568,
+	CXIDV_TELEM_HNI_RX_FRAGMENT = 569,
+	CXIDV_TELEM_HNI_RX_JABBER = 570,
+	CXIDV_TELEM_HNI_RX_OK_27 = 571,
+	CXIDV_TELEM_HNI_RX_OK_35 = 572,
+	CXIDV_TELEM_HNI_RX_OK_36_TO_63 = 573,
+	CXIDV_TELEM_HNI_RX_OK_64 = 574,
+	CXIDV_TELEM_HNI_RX_OK_65_TO_127 = 575,
+	CXIDV_TELEM_HNI_RX_OK_128_TO_255 = 576,
+	CXIDV_TELEM_HNI_RX_OK_256_TO_511 = 577,
+	CXIDV_TELEM_HNI_RX_OK_512_TO_1023 = 578,
+	CXIDV_TELEM_HNI_RX_OK_1024_TO_2047 = 579,
+	CXIDV_TELEM_HNI_RX_OK_2048_TO_4095 = 580,
+	CXIDV_TELEM_HNI_RX_OK_4096_TO_8191 = 581,
+	CXIDV_TELEM_HNI_RX_OK_8192_TO_MAX = 582,
+	CXIDV_TELEM_HNI_RX_OK_BAD_OP_CODE = 583,
+	CXIDV_TELEM_HNI_RX_OK_BROADCAST = 584,
+	CXIDV_TELEM_HNI_RX_OK_FLOW_CONTROL = 585,
+	CXIDV_TELEM_HNI_RX_OK_IEEE = 586,
+	CXIDV_TELEM_HNI_RX_OK_LEN_TYPE_ERROR = 587,
+	CXIDV_TELEM_HNI_RX_OK_MAC_CONTROL = 588,
+	CXIDV_TELEM_HNI_RX_OK_MULTICAST = 589,
+	CXIDV_TELEM_HNI_RX_OK_OPT = 590,
+	CXIDV_TELEM_HNI_RX_OK_TAGGED = 591,
+	CXIDV_TELEM_HNI_RX_OK_TOO_LONG = 592,
+	CXIDV_TELEM_HNI_RX_OK_UNDERSIZE = 593,
+	CXIDV_TELEM_HNI_RX_PAUSED_0 = 594,
+	CXIDV_TELEM_HNI_RX_PAUSED_1 = 595,
+	CXIDV_TELEM_HNI_RX_PAUSED_2 = 596,
+	CXIDV_TELEM_HNI_RX_PAUSED_3 = 597,
+	CXIDV_TELEM_HNI_RX_PAUSED_4 = 598,
+	CXIDV_TELEM_HNI_RX_PAUSED_5 = 599,
+	CXIDV_TELEM_HNI_RX_PAUSED_6 = 600,
+	CXIDV_TELEM_HNI_RX_PAUSED_7 = 601,
+	CXIDV_TELEM_HNI_RX_PAUSED_STD = 602,
+	CXIDV_TELEM_HNI_RX_STALL_IXE_FIFO = 603,
+	CXIDV_TELEM_HNI_RX_STALL_IXE_PKTBUF_0 = 604,
+	CXIDV_TELEM_HNI_RX_STALL_IXE_PKTBUF_1 = 605,
+	CXIDV_TELEM_HNI_RX_STALL_IXE_PKTBUF_2 = 606,
+	CXIDV_TELEM_HNI_RX_STALL_IXE_PKTBUF_3 = 607,
+	CXIDV_TELEM_HNI_RX_STALL_IXE_PKTBUF_4 = 608,
+	CXIDV_TELEM_HNI_RX_STALL_IXE_PKTBUF_5 = 609,
+	CXIDV_TELEM_HNI_RX_STALL_IXE_PKTBUF_6 = 610,
+	CXIDV_TELEM_HNI_RX_STALL_IXE_PKTBUF_7 = 611,
+	CXIDV_TELEM_HNI_STS_RX_BAD_OCTETS = 612,
+	CXIDV_TELEM_HNI_STS_RX_OCTETS_BCAST = 613,
+	CXIDV_TELEM_HNI_STS_RX_OCTETS_IEEE = 614,
+	CXIDV_TELEM_HNI_STS_RX_OCTETS_MULTI = 615,
+	CXIDV_TELEM_HNI_STS_RX_OCTETS_OPT = 616,
+	CXIDV_TELEM_HNI_STS_RX_OK_OCTETS = 617,
+	CXIDV_TELEM_HNI_STS_TX_BAD_OCTETS = 618,
+	CXIDV_TELEM_HNI_STS_TX_OCTETS_BCAST = 619,
+	CXIDV_TELEM_HNI_STS_TX_OCTETS_IEEE = 620,
+	CXIDV_TELEM_HNI_STS_TX_OCTETS_MULTI = 621,
+	CXIDV_TELEM_HNI_STS_TX_OCTETS_OPT = 622,
+	CXIDV_TELEM_HNI_STS_TX_OK_OCTETS = 623,
+	CXIDV_TELEM_HNI_TX_OK_27 = 624,
+	CXIDV_TELEM_HNI_TX_OK_35 = 625,
+	CXIDV_TELEM_HNI_TX_OK_36_TO_63 = 626,
+	CXIDV_TELEM_HNI_TX_OK_64 = 627,
+	CXIDV_TELEM_HNI_TX_OK_65_TO_127 = 628,
+	CXIDV_TELEM_HNI_TX_OK_128_TO_255 = 629,
+	CXIDV_TELEM_HNI_TX_OK_256_TO_511 = 630,
+	CXIDV_TELEM_HNI_TX_OK_512_TO_1023 = 631,
+	CXIDV_TELEM_HNI_TX_OK_1024_TO_2047 = 632,
+	CXIDV_TELEM_HNI_TX_OK_2048_TO_4095 = 633,
+	CXIDV_TELEM_HNI_TX_OK_4096_TO_8191 = 634,
+	CXIDV_TELEM_HNI_TX_OK_8192_TO_MAX = 635,
+	CXIDV_TELEM_HNI_TX_OK_BROADCAST = 636,
+	CXIDV_TELEM_HNI_TX_OK_IEEE = 637,
+	CXIDV_TELEM_HNI_TX_OK_MULTICAST = 638,
+	CXIDV_TELEM_HNI_TX_OK_OPT = 639,
+	CXIDV_TELEM_HNI_TX_OK_TAGGED = 640,
+	CXIDV_TELEM_HNI_TX_OPT_PADDED = 641,
+	CXIDV_TELEM_HNI_TX_OPT_SIZE_ERR = 642,
+	CXIDV_TELEM_HNI_TX_PAUSED_0 = 643,
+	CXIDV_TELEM_HNI_TX_PAUSED_1 = 644,
+	CXIDV_TELEM_HNI_TX_PAUSED_2 = 645,
+	CXIDV_TELEM_HNI_TX_PAUSED_3 = 646,
+	CXIDV_TELEM_HNI_TX_PAUSED_4 = 647,
+	CXIDV_TELEM_HNI_TX_PAUSED_5 = 648,
+	CXIDV_TELEM_HNI_TX_PAUSED_6 = 649,
+	CXIDV_TELEM_HNI_TX_PAUSED_7 = 650,
+	CXIDV_TELEM_HNI_TX_POISONED_IEEE = 651,
+	CXIDV_TELEM_HNI_TX_POISONED_OPT = 652,
+	CXIDV_TELEM_HNI_TX_STALL_LLR = 653,
+	CXIDV_TELEM_HNI_TX_STD_PADDED = 654,
+	CXIDV_TELEM_HNI_TX_STD_SIZE_ERR = 655,
+	CXIDV_TELEM_HNI_UCOR_ECC_ERR_CNTR = 656,
+	CXIDV_TELEM_IXE_DISP_AMO_CONFLICTS = 657,
+	CXIDV_TELEM_IXE_DISP_AMO_EVENTS = 658,
+	CXIDV_TELEM_IXE_DISP_ATU_FLUSH_REQS = 659,
+	CXIDV_TELEM_IXE_DISP_ATU_REQS = 660,
+	CXIDV_TELEM_IXE_DISP_ATU_RESPS = 661,
+	CXIDV_TELEM_IXE_DISP_ATU_RESPS_OK = 662,
+	CXIDV_TELEM_IXE_DISP_DMAWR_REQS = 663,
+	CXIDV_TELEM_IXE_DISP_DMAWR_RESPS = 664,
+	CXIDV_TELEM_IXE_DISP_DMAWR_RESPS_OK = 665,
+	CXIDV_TELEM_IXE_DISP_ETH_EVENTS = 666,
+	CXIDV_TELEM_IXE_DISP_LPE_AMOS = 667,
+	CXIDV_TELEM_IXE_DISP_LPE_AMOS_OK = 668,
+	CXIDV_TELEM_IXE_DISP_LPE_GETS = 669,
+	CXIDV_TELEM_IXE_DISP_LPE_GETS_OK = 670,
+	CXIDV_TELEM_IXE_DISP_LPE_PUTS = 671,
+	CXIDV_TELEM_IXE_DISP_LPE_PUTS_OK = 672,
+	CXIDV_TELEM_IXE_DISP_MST_GETS = 673,
+	CXIDV_TELEM_IXE_DISP_MST_GETS_OK = 674,
+	CXIDV_TELEM_IXE_DISP_MST_PUTS = 675,
+	CXIDV_TELEM_IXE_DISP_MST_PUTS_OK = 676,
+	CXIDV_TELEM_IXE_DISP_OXE_RESPS = 677,
+	CXIDV_TELEM_IXE_DISP_PCT_GETCOMP = 678,
+	CXIDV_TELEM_IXE_DISP_PUT_EVENTS = 679,
+	CXIDV_TELEM_IXE_DISP_RPU_ERR_REQS = 680,
+	CXIDV_TELEM_IXE_DISP_RPU_RESPS = 681,
+	CXIDV_TELEM_IXE_DISP_STALL_ATU_CDT = 682,
+	CXIDV_TELEM_IXE_DISP_STALL_ATU_FIFO = 683,
+	CXIDV_TELEM_IXE_DISP_STALL_CONFLICT = 684,
+	CXIDV_TELEM_IXE_DISP_STALL_ERR_FIFO = 685,
+	CXIDV_TELEM_IXE_DISP_STALL_GCOMP_FIFO = 686,
+	CXIDV_TELEM_IXE_DISP_STALL_GRR_ID = 687,
+	CXIDV_TELEM_IXE_DISP_STALL_MDID_CDTS = 688,
+	CXIDV_TELEM_IXE_DISP_STALL_MST_MATCH_FIFO = 689,
+	CXIDV_TELEM_IXE_DISP_STALL_PUT_RESP = 690,
+	CXIDV_TELEM_IXE_DISP_STALL_RESP_FIFO = 691,
+	CXIDV_TELEM_IXE_DISP_WR_CONFLICTS = 692,
+	CXIDV_TELEM_IXE_DMAWR_AMO_EX_INEXACT = 693,
+	CXIDV_TELEM_IXE_DMAWR_AMO_EX_INVALID = 694,
+	CXIDV_TELEM_IXE_DMAWR_AMO_EX_OVERFLOW = 695,
+	CXIDV_TELEM_IXE_DMAWR_AMO_EX_UNDERFLOW = 696,
+	CXIDV_TELEM_IXE_DMAWR_AMO_INVALID_OP = 697,
+	CXIDV_TELEM_IXE_DMAWR_AMO_LEN_ERR = 698,
+	CXIDV_TELEM_IXE_DMAWR_AMO_MISALIGNED = 699,
+	CXIDV_TELEM_IXE_DMAWR_CPU_AMO_REQS = 700,
+	CXIDV_TELEM_IXE_DMAWR_CPU_FTCH_AMO_REQS = 701,
+	CXIDV_TELEM_IXE_DMAWR_FLUSH_REQS = 702,
+	CXIDV_TELEM_IXE_DMAWR_NIC_AMO_REQS = 703,
+	CXIDV_TELEM_IXE_DMAWR_P_PASS_NP_CNT = 704,
+	CXIDV_TELEM_IXE_DMAWR_PCIE_ERR_POISONED = 705,
+	CXIDV_TELEM_IXE_DMAWR_PCIE_UNSUCCESS_CMPL = 706,
+	CXIDV_TELEM_IXE_DMAWR_REQ_NO_WRITE_REQS = 707,
+	CXIDV_TELEM_IXE_DMAWR_STALL_FTCH_AMO_CNT = 708,
+	CXIDV_TELEM_IXE_DMAWR_STALL_NP_CDT = 709,
+	CXIDV_TELEM_IXE_DMAWR_STALL_NP_REQ_CNT = 710,
+	CXIDV_TELEM_IXE_DMAWR_STALL_P_CDT = 711,
+	CXIDV_TELEM_IXE_DMAWR_WRITE_REQS = 712,
+	CXIDV_TELEM_IXE_GET_LEN_ERRORS = 713,
+	CXIDV_TELEM_IXE_HDR_CHECKSUM_ERRORS = 714,
+	CXIDV_TELEM_IXE_HDR_ECC_ERRORS = 715,
+	CXIDV_TELEM_IXE_HRP_REQ_ERRORS = 716,
+	CXIDV_TELEM_IXE_IP_OPTIONS_ERRORS = 717,
+	CXIDV_TELEM_IXE_IPV4_CHECKSUM_ERRORS = 718,
+	CXIDV_TELEM_IXE_MEM_COR_ERR_CNTR = 719,
+	CXIDV_TELEM_IXE_MEM_UCOR_ERR_CNTR = 720,
+	CXIDV_TELEM_IXE_PARSER_PAR_ERRORS = 721,
+	CXIDV_TELEM_IXE_PBUF_RD_ERRORS = 722,
+	CXIDV_TELEM_IXE_POOL_ECN_PKTS_0 = 723,
+	CXIDV_TELEM_IXE_POOL_ECN_PKTS_1 = 724,
+	CXIDV_TELEM_IXE_POOL_ECN_PKTS_2 = 725,
+	CXIDV_TELEM_IXE_POOL_ECN_PKTS_3 = 726,
+	CXIDV_TELEM_IXE_POOL_NO_ECN_PKTS_0 = 727,
+	CXIDV_TELEM_IXE_POOL_NO_ECN_PKTS_1 = 728,
+	CXIDV_TELEM_IXE_POOL_NO_ECN_PKTS_2 = 729,
+	CXIDV_TELEM_IXE_POOL_NO_ECN_PKTS_3 = 730,
+	CXIDV_TELEM_IXE_PORT_DFA_MISMATCH = 731,
+	CXIDV_TELEM_IXE_ROCE_ICRC_ERROR = 732,
+	CXIDV_TELEM_IXE_RX_ETH_SEG = 733,
+	CXIDV_TELEM_IXE_RX_IPV4_PKT = 734,
+	CXIDV_TELEM_IXE_RX_IPV6_PKT = 735,
+	CXIDV_TELEM_IXE_RX_PKT_DROP_IXE_PARSER = 736,
+	CXIDV_TELEM_IXE_RX_PKT_DROP_PCT = 737,
+	CXIDV_TELEM_IXE_RX_PKT_DROP_RMU_NORSP = 738,
+	CXIDV_TELEM_IXE_RX_PKT_DROP_RMU_WRSP = 739,
+	CXIDV_TELEM_IXE_RX_PKT_IPV4_OPTIONS = 740,
+	CXIDV_TELEM_IXE_RX_PKT_IPV6_OPTIONS = 741,
+	CXIDV_TELEM_IXE_RX_PTL_CONNMGMT_PKT = 742,
+	CXIDV_TELEM_IXE_RX_PTL_CONTINUATION_PKT = 743,
+	CXIDV_TELEM_IXE_RX_PTL_GEN_PKT = 744,
+	CXIDV_TELEM_IXE_RX_PTL_MR_MSGS = 745,
+	CXIDV_TELEM_IXE_RX_PTL_MSGS = 746,
+	CXIDV_TELEM_IXE_RX_PTL_MULTI_MSGS = 747,
+	CXIDV_TELEM_IXE_RX_PTL_RESPONSE_PKT = 748,
+	CXIDV_TELEM_IXE_RX_PTL_RESTRICTED_PKT = 749,
+	CXIDV_TELEM_IXE_RX_PTL_SMALLMSG_PKT = 750,
+	CXIDV_TELEM_IXE_RX_PTL_SML_AMO_PKT = 751,
+	CXIDV_TELEM_IXE_RX_PTL_SML_PKT = 752,
+	CXIDV_TELEM_IXE_RX_PTL_UNRESTRICTED_PKT = 753,
+	CXIDV_TELEM_IXE_RX_ROCE_PKT = 754,
+	CXIDV_TELEM_IXE_RX_ROCE_SEG = 755,
+	CXIDV_TELEM_IXE_RX_ROCE_SPSEG = 756,
+	CXIDV_TELEM_IXE_RX_TCP_PKT = 757,
+	CXIDV_TELEM_IXE_RX_UDP_PKT = 758,
+	CXIDV_TELEM_IXE_RX_UNRECOGNIZED_PKT = 759,
+	CXIDV_TELEM_IXE_TC_REQ_ECN_PKTS_0 = 760,
+	CXIDV_TELEM_IXE_TC_REQ_ECN_PKTS_1 = 761,
+	CXIDV_TELEM_IXE_TC_REQ_ECN_PKTS_2 = 762,
+	CXIDV_TELEM_IXE_TC_REQ_ECN_PKTS_3 = 763,
+	CXIDV_TELEM_IXE_TC_REQ_ECN_PKTS_4 = 764,
+	CXIDV_TELEM_IXE_TC_REQ_ECN_PKTS_5 = 765,
+	CXIDV_TELEM_IXE_TC_REQ_ECN_PKTS_6 = 766,
+	CXIDV_TELEM_IXE_TC_REQ_ECN_PKTS_7 = 767,
+	CXIDV_TELEM_IXE_TC_REQ_NO_ECN_PKTS_0 = 768,
+	CXIDV_TELEM_IXE_TC_REQ_NO_ECN_PKTS_1 = 769,
+	CXIDV_TELEM_IXE_TC_REQ_NO_ECN_PKTS_2 = 770,
+	CXIDV_TELEM_IXE_TC_REQ_NO_ECN_PKTS_3 = 771,
+	CXIDV_TELEM_IXE_TC_REQ_NO_ECN_PKTS_4 = 772,
+	CXIDV_TELEM_IXE_TC_REQ_NO_ECN_PKTS_5 = 773,
+	CXIDV_TELEM_IXE_TC_REQ_NO_ECN_PKTS_6 = 774,
+	CXIDV_TELEM_IXE_TC_REQ_NO_ECN_PKTS_7 = 775,
+	CXIDV_TELEM_IXE_TC_RSP_ECN_PKTS_0 = 776,
+	CXIDV_TELEM_IXE_TC_RSP_ECN_PKTS_1 = 777,
+	CXIDV_TELEM_IXE_TC_RSP_ECN_PKTS_2 = 778,
+	CXIDV_TELEM_IXE_TC_RSP_ECN_PKTS_3 = 779,
+	CXIDV_TELEM_IXE_TC_RSP_ECN_PKTS_4 = 780,
+	CXIDV_TELEM_IXE_TC_RSP_ECN_PKTS_5 = 781,
+	CXIDV_TELEM_IXE_TC_RSP_ECN_PKTS_6 = 782,
+	CXIDV_TELEM_IXE_TC_RSP_ECN_PKTS_7 = 783,
+	CXIDV_TELEM_IXE_TC_RSP_NO_ECN_PKTS_0 = 784,
+	CXIDV_TELEM_IXE_TC_RSP_NO_ECN_PKTS_1 = 785,
+	CXIDV_TELEM_IXE_TC_RSP_NO_ECN_PKTS_2 = 786,
+	CXIDV_TELEM_IXE_TC_RSP_NO_ECN_PKTS_3 = 787,
+	CXIDV_TELEM_IXE_TC_RSP_NO_ECN_PKTS_4 = 788,
+	CXIDV_TELEM_IXE_TC_RSP_NO_ECN_PKTS_5 = 789,
+	CXIDV_TELEM_IXE_TC_RSP_NO_ECN_PKTS_6 = 790,
+	CXIDV_TELEM_IXE_TC_RSP_NO_ECN_PKTS_7 = 791,
+	CXIDV_TELEM_LPE_AMO_CMDS = 792,
+	CXIDV_TELEM_LPE_APPEND_CMDS_0 = 793,
+	CXIDV_TELEM_LPE_APPEND_CMDS_1 = 794,
+	CXIDV_TELEM_LPE_APPEND_CMDS_2 = 795,
+	CXIDV_TELEM_LPE_APPEND_CMDS_3 = 796,
+	CXIDV_TELEM_LPE_APPEND_SUCCESS_0 = 797,
+	CXIDV_TELEM_LPE_APPEND_SUCCESS_1 = 798,
+	CXIDV_TELEM_LPE_APPEND_SUCCESS_2 = 799,
+	CXIDV_TELEM_LPE_APPEND_SUCCESS_3 = 800,
+	CXIDV_TELEM_LPE_CFG_EVENT_CNTS_OVF_CNT = 801,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_SHARED_0 = 802,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_SHARED_1 = 803,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_SHARED_2 = 804,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_SHARED_3 = 805,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_SHARED_ALLOCATED_0 = 806,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_SHARED_ALLOCATED_1 = 807,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_SHARED_ALLOCATED_2 = 808,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_SHARED_ALLOCATED_3 = 809,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_TOTAL_0 = 810,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_TOTAL_1 = 811,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_TOTAL_2 = 812,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_TOTAL_3 = 813,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_TOTAL_ALLOCATED_0 = 814,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_TOTAL_ALLOCATED_1 = 815,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_TOTAL_ALLOCATED_2 = 816,
+	CXIDV_TELEM_LPE_CFG_PE_LE_SHARED_NUM_TOTAL_ALLOCATED_3 = 817,
+	CXIDV_TELEM_LPE_CYC_BLOCKED_IXE_GET = 818,
+	CXIDV_TELEM_LPE_CYC_BLOCKED_IXE_PUT = 819,
+	CXIDV_TELEM_LPE_CYC_BLOCKED_LOSSLESS = 820,
+	CXIDV_TELEM_LPE_CYC_NO_RDY_CDTS = 821,
+	CXIDV_TELEM_LPE_CYC_RRQ_BLOCKED_0 = 822,
+	CXIDV_TELEM_LPE_CYC_RRQ_BLOCKED_1 = 823,
+	CXIDV_TELEM_LPE_CYC_RRQ_BLOCKED_2 = 824,
+	CXIDV_TELEM_LPE_CYC_RRQ_BLOCKED_3 = 825,
+	CXIDV_TELEM_LPE_ERR_ENTRY_NOT_FOUND_CANT_ALLOC_UNEXPECTED = 826,
+	CXIDV_TELEM_LPE_ERR_ENTRY_NOT_FOUND_EQ_FULL = 827,
+	CXIDV_TELEM_LPE_ERR_ENTRY_NOT_FOUND_ETHERNET = 828,
+	CXIDV_TELEM_LPE_ERR_ENTRY_NOT_FOUND_NO_MATCH_IN_OVERFLOW = 829,
+	CXIDV_TELEM_LPE_ERR_ENTRY_NOT_FOUND_REQ_EMPTY = 830,
+	CXIDV_TELEM_LPE_ERR_ENTRY_NOT_FOUND_UNLINK_FAILED = 831,
+	CXIDV_TELEM_LPE_ERR_EQ_DISABLED = 832,
+	CXIDV_TELEM_LPE_ERR_ILLEGAL_OP = 833,
+	CXIDV_TELEM_LPE_ERR_INVALID_ENDPOINT = 834,
+	CXIDV_TELEM_LPE_ERR_NO_SPACE_APPEND = 835,
+	CXIDV_TELEM_LPE_ERR_NO_SPACE_NET = 836,
+	CXIDV_TELEM_LPE_ERR_OP_VIOLATION = 837,
+	CXIDV_TELEM_LPE_ERR_PT_DISABLED_CANT_ALLOC_UNEXPECTED = 838,
+	CXIDV_TELEM_LPE_ERR_PT_DISABLED_EQ_FULL = 839,
+	CXIDV_TELEM_LPE_ERR_PT_DISABLED_NO_MATCH_IN_OVERFLOW = 840,
+	CXIDV_TELEM_LPE_ERR_PT_DISABLED_REQ_EMPTY = 841,
+	CXIDV_TELEM_LPE_ERR_PTLTE_SW_MANAGED = 842,
+	CXIDV_TELEM_LPE_ERR_RESTRICTED_UNICAST = 843,
+	CXIDV_TELEM_LPE_ERR_SEARCH_NO_MATCH = 844,
+	CXIDV_TELEM_LPE_ERR_SETSTATE_NO_MATCH = 845,
+	CXIDV_TELEM_LPE_ERR_SRC_ERROR = 846,
+	CXIDV_TELEM_LPE_EVENT_ATOMIC_OVERFLOW = 847,
+	CXIDV_TELEM_LPE_EVENT_FETCH_ATOMIC_OVERFLOW = 848,
+	CXIDV_TELEM_LPE_EVENT_GET_OVERFLOW = 849,
+	CXIDV_TELEM_LPE_EVENT_LINK = 850,
+	CXIDV_TELEM_LPE_EVENT_PUT_OVERFLOW = 851,
+	CXIDV_TELEM_LPE_EVENT_RENDEZVOUS = 852,
+	CXIDV_TELEM_LPE_EVENT_SEARCH = 853,
+	CXIDV_TELEM_LPE_EVENT_STATECHANGE = 854,
+	CXIDV_TELEM_LPE_EVENT_UNLINK = 855,
+	CXIDV_TELEM_LPE_FAIL_CNTR = 856,
+	CXIDV_TELEM_LPE_FAMO_CMDS = 857,
+	CXIDV_TELEM_LPE_GET_CMDS = 858,
+	CXIDV_TELEM_LPE_MEM_COR_ERR_CNTR = 859,
+	CXIDV_TELEM_LPE_MEM_UCOR_ERR_CNTR = 860,
+	CXIDV_TELEM_LPE_NET_MATCH_LOCAL_0 = 861,
+	CXIDV_TELEM_LPE_NET_MATCH_LOCAL_1 = 862,
+	CXIDV_TELEM_LPE_NET_MATCH_LOCAL_2 = 863,
+	CXIDV_TELEM_LPE_NET_MATCH_LOCAL_3 = 864,
+	CXIDV_TELEM_LPE_NET_MATCH_OVERFLOW_0 = 865,
+	CXIDV_TELEM_LPE_NET_MATCH_OVERFLOW_1 = 866,
+	CXIDV_TELEM_LPE_NET_MATCH_OVERFLOW_2 = 867,
+	CXIDV_TELEM_LPE_NET_MATCH_OVERFLOW_3 = 868,
+	CXIDV_TELEM_LPE_NET_MATCH_PRIORITY_0 = 869,
+	CXIDV_TELEM_LPE_NET_MATCH_PRIORITY_1 = 870,
+	CXIDV_TELEM_LPE_NET_MATCH_PRIORITY_2 = 871,
+	CXIDV_TELEM_LPE_NET_MATCH_PRIORITY_3 = 872,
+	CXIDV_TELEM_LPE_NET_MATCH_REQUEST_0 = 873,
+	CXIDV_TELEM_LPE_NET_MATCH_REQUEST_1 = 874,
+	CXIDV_TELEM_LPE_NET_MATCH_REQUEST_2 = 875,
+	CXIDV_TELEM_LPE_NET_MATCH_REQUEST_3 = 876,
+	CXIDV_TELEM_LPE_NET_MATCH_REQUESTS_0 = 877,
+	CXIDV_TELEM_LPE_NET_MATCH_REQUESTS_1 = 878,
+	CXIDV_TELEM_LPE_NET_MATCH_REQUESTS_2 = 879,
+	CXIDV_TELEM_LPE_NET_MATCH_REQUESTS_3 = 880,
+	CXIDV_TELEM_LPE_NET_MATCH_SUCCESS_0 = 881,
+	CXIDV_TELEM_LPE_NET_MATCH_SUCCESS_1 = 882,
+	CXIDV_TELEM_LPE_NET_MATCH_SUCCESS_2 = 883,
+	CXIDV_TELEM_LPE_NET_MATCH_SUCCESS_3 = 884,
+	CXIDV_TELEM_LPE_NET_MATCH_USEONCE_0 = 885,
+	CXIDV_TELEM_LPE_NET_MATCH_USEONCE_1 = 886,
+	CXIDV_TELEM_LPE_NET_MATCH_USEONCE_2 = 887,
+	CXIDV_TELEM_LPE_NET_MATCH_USEONCE_3 = 888,
+	CXIDV_TELEM_LPE_NUM_TRUNCATED_0 = 889,
+	CXIDV_TELEM_LPE_NUM_TRUNCATED_1 = 890,
+	CXIDV_TELEM_LPE_NUM_TRUNCATED_2 = 891,
+	CXIDV_TELEM_LPE_NUM_TRUNCATED_3 = 892,
+	CXIDV_TELEM_LPE_PLEC_ALLOCS = 893,
+	CXIDV_TELEM_LPE_PLEC_FREES = 894,
+	CXIDV_TELEM_LPE_PLEC_FREES_CSR = 895,
+	CXIDV_TELEM_LPE_PLEC_HITS = 896,
+	CXIDV_TELEM_LPE_PUT_CMDS = 897,
+	CXIDV_TELEM_LPE_RENDEZVOUS_PUT_CMDS = 898,
+	CXIDV_TELEM_LPE_RNDZV_PUTS_0 = 899,
+	CXIDV_TELEM_LPE_RNDZV_PUTS_1 = 900,
+	CXIDV_TELEM_LPE_RNDZV_PUTS_2 = 901,
+	CXIDV_TELEM_LPE_RNDZV_PUTS_3 = 902,
+	CXIDV_TELEM_LPE_RNDZV_PUTS_OFFLOADED_0 = 903,
+	CXIDV_TELEM_LPE_RNDZV_PUTS_OFFLOADED_1 = 904,
+	CXIDV_TELEM_LPE_RNDZV_PUTS_OFFLOADED_2 = 905,
+	CXIDV_TELEM_LPE_RNDZV_PUTS_OFFLOADED_3 = 906,
+	CXIDV_TELEM_LPE_SEARCH_CMDS = 907,
+	CXIDV_TELEM_LPE_SEARCH_DELETE_CMDS = 908,
+	CXIDV_TELEM_LPE_SEARCH_DELETE_FAIL = 909,
+	CXIDV_TELEM_LPE_SEARCH_DELETE_SUCCESS = 910,
+	CXIDV_TELEM_LPE_SEARCH_FAIL = 911,
+	CXIDV_TELEM_LPE_SEARCH_NID_ANY_0 = 912,
+	CXIDV_TELEM_LPE_SEARCH_NID_ANY_1 = 913,
+	CXIDV_TELEM_LPE_SEARCH_NID_ANY_2 = 914,
+	CXIDV_TELEM_LPE_SEARCH_NID_ANY_3 = 915,
+	CXIDV_TELEM_LPE_SEARCH_PID_ANY_0 = 916,
+	CXIDV_TELEM_LPE_SEARCH_PID_ANY_1 = 917,
+	CXIDV_TELEM_LPE_SEARCH_PID_ANY_2 = 918,
+	CXIDV_TELEM_LPE_SEARCH_PID_ANY_3 = 919,
+	CXIDV_TELEM_LPE_SEARCH_RANK_ANY_0 = 920,
+	CXIDV_TELEM_LPE_SEARCH_RANK_ANY_1 = 921,
+	CXIDV_TELEM_LPE_SEARCH_RANK_ANY_2 = 922,
+	CXIDV_TELEM_LPE_SEARCH_RANK_ANY_3 = 923,
+	CXIDV_TELEM_LPE_SEARCH_SUCCESS = 924,
+	CXIDV_TELEM_LPE_SETSTATE_CMDS_0 = 925,
+	CXIDV_TELEM_LPE_SETSTATE_CMDS_1 = 926,
+	CXIDV_TELEM_LPE_SETSTATE_CMDS_2 = 927,
+	CXIDV_TELEM_LPE_SETSTATE_CMDS_3 = 928,
+	CXIDV_TELEM_LPE_SETSTATE_SUCCESS_0 = 929,
+	CXIDV_TELEM_LPE_SETSTATE_SUCCESS_1 = 930,
+	CXIDV_TELEM_LPE_SETSTATE_SUCCESS_2 = 931,
+	CXIDV_TELEM_LPE_SETSTATE_SUCCESS_3 = 932,
+	CXIDV_TELEM_LPE_STS_APP_MATCH_ATTEMPTS_0 = 933,
+	CXIDV_TELEM_LPE_STS_APP_MATCH_ATTEMPTS_1 = 934,
+	CXIDV_TELEM_LPE_STS_APP_MATCH_ATTEMPTS_2 = 935,
+	CXIDV_TELEM_LPE_STS_APP_MATCH_ATTEMPTS_3 = 936,
+	CXIDV_TELEM_LPE_STS_APP_MAX_ATTEMPTS_MAX_0 = 937,
+	CXIDV_TELEM_LPE_STS_APP_MAX_ATTEMPTS_MAX_1 = 938,
+	CXIDV_TELEM_LPE_STS_APP_MAX_ATTEMPTS_MAX_2 = 939,
+	CXIDV_TELEM_LPE_STS_APP_MAX_ATTEMPTS_MAX_3 = 940,
+	CXIDV_TELEM_LPE_STS_APP_MAX_ATTEMPTS_NUM_PBUF_ENTRIES_0 = 941,
+	CXIDV_TELEM_LPE_STS_APP_MAX_ATTEMPTS_NUM_PBUF_ENTRIES_1 = 942,
+	CXIDV_TELEM_LPE_STS_APP_MAX_ATTEMPTS_NUM_PBUF_ENTRIES_2 = 943,
+	CXIDV_TELEM_LPE_STS_APP_MAX_ATTEMPTS_NUM_PBUF_ENTRIES_3 = 944,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_LOAD_0 = 945,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_LOAD_1 = 946,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_LOAD_2 = 947,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_LOAD_3 = 948,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_MAX_0 = 949,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_MAX_1 = 950,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_MAX_2 = 951,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_MAX_3 = 952,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_PTLTE_LOAD_0 = 953,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_PTLTE_LOAD_1 = 954,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_PTLTE_LOAD_2 = 955,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_PTLTE_LOAD_3 = 956,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_PTLTE_MAX_0 = 957,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_PTLTE_MAX_1 = 958,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_PTLTE_MAX_2 = 959,
+	CXIDV_TELEM_LPE_STS_LOAD_STATS_PTLTE_MAX_3 = 960,
+	CXIDV_TELEM_LPE_STS_NET_MATCH_ATTEMPTS_0 = 961,
+	CXIDV_TELEM_LPE_STS_NET_MATCH_ATTEMPTS_1 = 962,
+	CXIDV_TELEM_LPE_STS_NET_MATCH_ATTEMPTS_2 = 963,
+	CXIDV_TELEM_LPE_STS_NET_MATCH_ATTEMPTS_3 = 964,
+	CXIDV_TELEM_LPE_STS_NET_MAX_ATTEMPTS_MAX_0 = 965,
+	CXIDV_TELEM_LPE_STS_NET_MAX_ATTEMPTS_MAX_1 = 966,
+	CXIDV_TELEM_LPE_STS_NET_MAX_ATTEMPTS_MAX_2 = 967,
+	CXIDV_TELEM_LPE_STS_NET_MAX_ATTEMPTS_MAX_3 = 968,
+	CXIDV_TELEM_LPE_STS_NET_MAX_ATTEMPTS_NUM_PBUF_ENTRIES_0 = 969,
+	CXIDV_TELEM_LPE_STS_NET_MAX_ATTEMPTS_NUM_PBUF_ENTRIES_1 = 970,
+	CXIDV_TELEM_LPE_STS_NET_MAX_ATTEMPTS_NUM_PBUF_ENTRIES_2 = 971,
+	CXIDV_TELEM_LPE_STS_NET_MAX_ATTEMPTS_NUM_PBUF_ENTRIES_3 = 972,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_0 = 973,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_1 = 974,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_2 = 975,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_3 = 976,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_4 = 977,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_5 = 978,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_6 = 979,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_7 = 980,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_8 = 981,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_9 = 982,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_10 = 983,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_11 = 984,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_12 = 985,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_13 = 986,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_14 = 987,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_15 = 988,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_16 = 989,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_17 = 990,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_18 = 991,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_19 = 992,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_20 = 993,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_21 = 994,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_22 = 995,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_23 = 996,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_24 = 997,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_25 = 998,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_26 = 999,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_27 = 1000,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_28 = 1001,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_29 = 1002,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_30 = 1003,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_31 = 1004,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_32 = 1005,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_33 = 1006,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_34 = 1007,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_35 = 1008,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_36 = 1009,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_37 = 1010,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_38 = 1011,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_39 = 1012,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_40 = 1013,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_41 = 1014,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_42 = 1015,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_43 = 1016,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_44 = 1017,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_45 = 1018,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_46 = 1019,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_47 = 1020,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_48 = 1021,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_49 = 1022,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_50 = 1023,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_51 = 1024,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_52 = 1025,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_53 = 1026,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_54 = 1027,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_55 = 1028,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_56 = 1029,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_57 = 1030,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_58 = 1031,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_59 = 1032,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_60 = 1033,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_61 = 1034,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_62 = 1035,
+	CXIDV_TELEM_LPE_STS_PE_LE_ALLOC_NUM_ALLOCATED_63 = 1036,
+	CXIDV_TELEM_LPE_SUCCESS_CNTR = 1037,
+	CXIDV_TELEM_LPE_UNEXPECTED_GET_AMO_0 = 1038,
+	CXIDV_TELEM_LPE_UNEXPECTED_GET_AMO_1 = 1039,
+	CXIDV_TELEM_LPE_UNEXPECTED_GET_AMO_2 = 1040,
+	CXIDV_TELEM_LPE_UNEXPECTED_GET_AMO_3 = 1041,
+	CXIDV_TELEM_LPE_UNLINK_CMDS = 1042,
+	CXIDV_TELEM_LPE_UNLINK_SUCCESS = 1043,
+	CXIDV_TELEM_MB_CFG_EVENT_CNTS_OVF_CNT = 1044,
+	CXIDV_TELEM_MB_CMC_AXI_RD_REQUESTS_0 = 1045,
+	CXIDV_TELEM_MB_CMC_AXI_RD_REQUESTS_1 = 1046,
+	CXIDV_TELEM_MB_CMC_AXI_RD_REQUESTS_2 = 1047,
+	CXIDV_TELEM_MB_CMC_AXI_RD_REQUESTS_3 = 1048,
+	CXIDV_TELEM_MB_CMC_AXI_WR_REQUESTS_0 = 1049,
+	CXIDV_TELEM_MB_CMC_AXI_WR_REQUESTS_1 = 1050,
+	CXIDV_TELEM_MB_CMC_AXI_WR_REQUESTS_2 = 1051,
+	CXIDV_TELEM_MB_CMC_AXI_WR_REQUESTS_3 = 1052,
+	CXIDV_TELEM_MB_CQ_LSA0_TRIGGER_EVENTS_0 = 1053,
+	CXIDV_TELEM_MB_CQ_LSA0_TRIGGER_EVENTS_1 = 1054,
+	CXIDV_TELEM_MB_CQ_LSA1_TRIGGER_EVENTS_0 = 1055,
+	CXIDV_TELEM_MB_CQ_LSA1_TRIGGER_EVENTS_1 = 1056,
+	CXIDV_TELEM_MB_CRMC_AXI_RD_REQUESTS_0 = 1057,
+	CXIDV_TELEM_MB_CRMC_AXI_RD_REQUESTS_1 = 1058,
+	CXIDV_TELEM_MB_CRMC_AXI_RD_REQUESTS_2 = 1059,
+	CXIDV_TELEM_MB_CRMC_AXI_WR_REQUESTS_0 = 1060,
+	CXIDV_TELEM_MB_CRMC_AXI_WR_REQUESTS_1 = 1061,
+	CXIDV_TELEM_MB_CRMC_AXI_WR_REQUESTS_2 = 1062,
+	CXIDV_TELEM_MB_CRMC_RD_ERROR_0 = 1063,
+	CXIDV_TELEM_MB_CRMC_RD_ERROR_1 = 1064,
+	CXIDV_TELEM_MB_CRMC_RD_ERROR_2 = 1065,
+	CXIDV_TELEM_MB_CRMC_RING_MBE_0 = 1066,
+	CXIDV_TELEM_MB_CRMC_RING_MBE_1 = 1067,
+	CXIDV_TELEM_MB_CRMC_RING_MBE_2 = 1068,
+	CXIDV_TELEM_MB_CRMC_RING_RD_REQUESTS_0 = 1069,
+	CXIDV_TELEM_MB_CRMC_RING_RD_REQUESTS_1 = 1070,
+	CXIDV_TELEM_MB_CRMC_RING_RD_REQUESTS_2 = 1071,
+	CXIDV_TELEM_MB_CRMC_RING_SBE_0 = 1072,
+	CXIDV_TELEM_MB_CRMC_RING_SBE_1 = 1073,
+	CXIDV_TELEM_MB_CRMC_RING_SBE_2 = 1074,
+	CXIDV_TELEM_MB_CRMC_RING_WR_REQUESTS_0 = 1075,
+	CXIDV_TELEM_MB_CRMC_RING_WR_REQUESTS_1 = 1076,
+	CXIDV_TELEM_MB_CRMC_RING_WR_REQUESTS_2 = 1077,
+	CXIDV_TELEM_MB_CRMC_WR_ERROR_0 = 1078,
+	CXIDV_TELEM_MB_CRMC_WR_ERROR_1 = 1079,
+	CXIDV_TELEM_MB_CRMC_WR_ERROR_2 = 1080,
+	CXIDV_TELEM_MB_EE_LSA0_TRIGGER_EVENTS_0 = 1081,
+	CXIDV_TELEM_MB_EE_LSA0_TRIGGER_EVENTS_1 = 1082,
+	CXIDV_TELEM_MB_EE_LSA1_TRIGGER_EVENTS_0 = 1083,
+	CXIDV_TELEM_MB_EE_LSA1_TRIGGER_EVENTS_1 = 1084,
+	CXIDV_TELEM_MB_IXE_LSA0_TRIGGER_EVENTS_0 = 1085,
+	CXIDV_TELEM_MB_IXE_LSA0_TRIGGER_EVENTS_1 = 1086,
+	CXIDV_TELEM_MB_IXE_LSA1_TRIGGER_EVENTS_0 = 1087,
+	CXIDV_TELEM_MB_IXE_LSA1_TRIGGER_EVENTS_1 = 1088,
+	CXIDV_TELEM_MB_JAI_AXI_RD_REQUESTS = 1089,
+	CXIDV_TELEM_MB_JAI_AXI_WR_REQUESTS = 1090,
+	CXIDV_TELEM_MB_MB_LSA0_TRIGGER_EVENTS_0 = 1091,
+	CXIDV_TELEM_MB_MB_LSA0_TRIGGER_EVENTS_1 = 1092,
+	CXIDV_TELEM_MB_MB_LSA1_TRIGGER_EVENTS_0 = 1093,
+	CXIDV_TELEM_MB_MB_LSA1_TRIGGER_EVENTS_1 = 1094,
+	CXIDV_TELEM_MST_ALLOCATIONS = 1095,
+	CXIDV_TELEM_MST_ERR_CANCELLED = 1096,
+	CXIDV_TELEM_MST_MEM_COR_ERR_CNTR = 1097,
+	CXIDV_TELEM_MST_MEM_UCOR_ERR_CNTR = 1098,
+	CXIDV_TELEM_MST_REQUESTS = 1099,
+	CXIDV_TELEM_MST_STALLED_WAITING_EE_CRDTS = 1100,
+	CXIDV_TELEM_MST_STALLED_WAITING_FOR_LPE = 1101,
+	CXIDV_TELEM_MST_STALLED_WAITING_GET_CRDTS = 1102,
+	CXIDV_TELEM_MST_STALLED_WAITING_PUT_CRDTS = 1103,
+	CXIDV_TELEM_MST_STS_NUM_REQ = 1104,
+	CXIDV_TELEM_OXE_CHANNEL_IDLE = 1105,
+	CXIDV_TELEM_OXE_ERR_INVALID_AC = 1106,
+	CXIDV_TELEM_OXE_ERR_NO_TRANSLATION = 1107,
+	CXIDV_TELEM_OXE_ERR_PAGE_PERM = 1108,
+	CXIDV_TELEM_OXE_ERR_PAGE_REQ = 1109,
+	CXIDV_TELEM_OXE_ERR_PCI_CMPL = 1110,
+	CXIDV_TELEM_OXE_ERR_PCI_EP = 1111,
+	CXIDV_TELEM_OXE_ERR_TA_ERROR = 1112,
+	CXIDV_TELEM_OXE_IGNORE_ERRS = 1113,
+	CXIDV_TELEM_OXE_IOI_DMA = 1114,
+	CXIDV_TELEM_OXE_IOI_PKTS_ORDERED = 1115,
+	CXIDV_TELEM_OXE_IOI_PKTS_UNORDERED = 1116,
+	CXIDV_TELEM_OXE_MCU_MEAS_0 = 1117,
+	CXIDV_TELEM_OXE_MCU_MEAS_1 = 1118,
+	CXIDV_TELEM_OXE_MCU_MEAS_2 = 1119,
+	CXIDV_TELEM_OXE_MCU_MEAS_3 = 1120,
+	CXIDV_TELEM_OXE_MCU_MEAS_4 = 1121,
+	CXIDV_TELEM_OXE_MCU_MEAS_5 = 1122,
+	CXIDV_TELEM_OXE_MCU_MEAS_6 = 1123,
+	CXIDV_TELEM_OXE_MCU_MEAS_7 = 1124,
+	CXIDV_TELEM_OXE_MCU_MEAS_8 = 1125,
+	CXIDV_TELEM_OXE_MCU_MEAS_9 = 1126,
+	CXIDV_TELEM_OXE_MCU_MEAS_10 = 1127,
+	CXIDV_TELEM_OXE_MCU_MEAS_11 = 1128,
+	CXIDV_TELEM_OXE_MCU_MEAS_12 = 1129,
+	CXIDV_TELEM_OXE_MCU_MEAS_13 = 1130,
+	CXIDV_TELEM_OXE_MCU_MEAS_14 = 1131,
+	CXIDV_TELEM_OXE_MCU_MEAS_15 = 1132,
+	CXIDV_TELEM_OXE_MCU_MEAS_16 = 1133,
+	CXIDV_TELEM_OXE_MCU_MEAS_17 = 1134,
+	CXIDV_TELEM_OXE_MCU_MEAS_18 = 1135,
+	CXIDV_TELEM_OXE_MCU_MEAS_19 = 1136,
+	CXIDV_TELEM_OXE_MCU_MEAS_20 = 1137,
+	CXIDV_TELEM_OXE_MCU_MEAS_21 = 1138,
+	CXIDV_TELEM_OXE_MCU_MEAS_22 = 1139,
+	CXIDV_TELEM_OXE_MCU_MEAS_23 = 1140,
+	CXIDV_TELEM_OXE_MCU_MEAS_24 = 1141,
+	CXIDV_TELEM_OXE_MCU_MEAS_25 = 1142,
+	CXIDV_TELEM_OXE_MCU_MEAS_26 = 1143,
+	CXIDV_TELEM_OXE_MCU_MEAS_27 = 1144,
+	CXIDV_TELEM_OXE_MCU_MEAS_28 = 1145,
+	CXIDV_TELEM_OXE_MCU_MEAS_29 = 1146,
+	CXIDV_TELEM_OXE_MCU_MEAS_30 = 1147,
+	CXIDV_TELEM_OXE_MCU_MEAS_31 = 1148,
+	CXIDV_TELEM_OXE_MCU_MEAS_32 = 1149,
+	CXIDV_TELEM_OXE_MCU_MEAS_33 = 1150,
+	CXIDV_TELEM_OXE_MCU_MEAS_34 = 1151,
+	CXIDV_TELEM_OXE_MCU_MEAS_35 = 1152,
+	CXIDV_TELEM_OXE_MCU_MEAS_36 = 1153,
+	CXIDV_TELEM_OXE_MCU_MEAS_37 = 1154,
+	CXIDV_TELEM_OXE_MCU_MEAS_38 = 1155,
+	CXIDV_TELEM_OXE_MCU_MEAS_39 = 1156,
+	CXIDV_TELEM_OXE_MCU_MEAS_40 = 1157,
+	CXIDV_TELEM_OXE_MCU_MEAS_41 = 1158,
+	CXIDV_TELEM_OXE_MCU_MEAS_42 = 1159,
+	CXIDV_TELEM_OXE_MCU_MEAS_43 = 1160,
+	CXIDV_TELEM_OXE_MCU_MEAS_44 = 1161,
+	CXIDV_TELEM_OXE_MCU_MEAS_45 = 1162,
+	CXIDV_TELEM_OXE_MCU_MEAS_46 = 1163,
+	CXIDV_TELEM_OXE_MCU_MEAS_47 = 1164,
+	CXIDV_TELEM_OXE_MCU_MEAS_48 = 1165,
+	CXIDV_TELEM_OXE_MCU_MEAS_49 = 1166,
+	CXIDV_TELEM_OXE_MCU_MEAS_50 = 1167,
+	CXIDV_TELEM_OXE_MCU_MEAS_51 = 1168,
+	CXIDV_TELEM_OXE_MCU_MEAS_52 = 1169,
+	CXIDV_TELEM_OXE_MCU_MEAS_53 = 1170,
+	CXIDV_TELEM_OXE_MCU_MEAS_54 = 1171,
+	CXIDV_TELEM_OXE_MCU_MEAS_55 = 1172,
+	CXIDV_TELEM_OXE_MCU_MEAS_56 = 1173,
+	CXIDV_TELEM_OXE_MCU_MEAS_57 = 1174,
+	CXIDV_TELEM_OXE_MCU_MEAS_58 = 1175,
+	CXIDV_TELEM_OXE_MCU_MEAS_59 = 1176,
+	CXIDV_TELEM_OXE_MCU_MEAS_60 = 1177,
+	CXIDV_TELEM_OXE_MCU_MEAS_61 = 1178,
+	CXIDV_TELEM_OXE_MCU_MEAS_62 = 1179,
+	CXIDV_TELEM_OXE_MCU_MEAS_63 = 1180,
+	CXIDV_TELEM_OXE_MCU_MEAS_64 = 1181,
+	CXIDV_TELEM_OXE_MCU_MEAS_65 = 1182,
+	CXIDV_TELEM_OXE_MCU_MEAS_66 = 1183,
+	CXIDV_TELEM_OXE_MCU_MEAS_67 = 1184,
+	CXIDV_TELEM_OXE_MCU_MEAS_68 = 1185,
+	CXIDV_TELEM_OXE_MCU_MEAS_69 = 1186,
+	CXIDV_TELEM_OXE_MCU_MEAS_70 = 1187,
+	CXIDV_TELEM_OXE_MCU_MEAS_71 = 1188,
+	CXIDV_TELEM_OXE_MCU_MEAS_72 = 1189,
+	CXIDV_TELEM_OXE_MCU_MEAS_73 = 1190,
+	CXIDV_TELEM_OXE_MCU_MEAS_74 = 1191,
+	CXIDV_TELEM_OXE_MCU_MEAS_75 = 1192,
+	CXIDV_TELEM_OXE_MCU_MEAS_76 = 1193,
+	CXIDV_TELEM_OXE_MCU_MEAS_77 = 1194,
+	CXIDV_TELEM_OXE_MCU_MEAS_78 = 1195,
+	CXIDV_TELEM_OXE_MCU_MEAS_79 = 1196,
+	CXIDV_TELEM_OXE_MCU_MEAS_80 = 1197,
+	CXIDV_TELEM_OXE_MCU_MEAS_81 = 1198,
+	CXIDV_TELEM_OXE_MCU_MEAS_82 = 1199,
+	CXIDV_TELEM_OXE_MCU_MEAS_83 = 1200,
+	CXIDV_TELEM_OXE_MCU_MEAS_84 = 1201,
+	CXIDV_TELEM_OXE_MCU_MEAS_85 = 1202,
+	CXIDV_TELEM_OXE_MCU_MEAS_86 = 1203,
+	CXIDV_TELEM_OXE_MCU_MEAS_87 = 1204,
+	CXIDV_TELEM_OXE_MCU_MEAS_88 = 1205,
+	CXIDV_TELEM_OXE_MCU_MEAS_89 = 1206,
+	CXIDV_TELEM_OXE_MCU_MEAS_90 = 1207,
+	CXIDV_TELEM_OXE_MCU_MEAS_91 = 1208,
+	CXIDV_TELEM_OXE_MCU_MEAS_92 = 1209,
+	CXIDV_TELEM_OXE_MCU_MEAS_93 = 1210,
+	CXIDV_TELEM_OXE_MCU_MEAS_94 = 1211,
+	CXIDV_TELEM_OXE_MCU_MEAS_95 = 1212,
+	CXIDV_TELEM_OXE_MEM_COR_ERR_CNTR = 1213,
+	CXIDV_TELEM_OXE_MEM_UCOR_ERR_CNTR = 1214,
+	CXIDV_TELEM_OXE_NUM_HRP_CMDS = 1215,
+	CXIDV_TELEM_OXE_PRF_SET0_OCC_HIST_BIN0 = 1216,
+	CXIDV_TELEM_OXE_PRF_SET0_OCC_HIST_BIN1 = 1217,
+	CXIDV_TELEM_OXE_PRF_SET0_OCC_HIST_BIN2 = 1218,
+	CXIDV_TELEM_OXE_PRF_SET0_OCC_HIST_BIN3 = 1219,
+	CXIDV_TELEM_OXE_PRF_SET0_PKTBUF_NA = 1220,
+	CXIDV_TELEM_OXE_PRF_SET0_SMT_NA = 1221,
+	CXIDV_TELEM_OXE_PRF_SET0_SPT_NA = 1222,
+	CXIDV_TELEM_OXE_PRF_SET0_SRB_NA = 1223,
+	CXIDV_TELEM_OXE_PRF_SET0_ST_DMA_MDR = 1224,
+	CXIDV_TELEM_OXE_PRF_SET0_ST_DMA_UPD = 1225,
+	CXIDV_TELEM_OXE_PRF_SET0_ST_HEADER = 1226,
+	CXIDV_TELEM_OXE_PRF_SET0_ST_PCT_IDX_WAIT = 1227,
+	CXIDV_TELEM_OXE_PRF_SET0_ST_PKTBUF_GNT = 1228,
+	CXIDV_TELEM_OXE_PRF_SET0_ST_PKTBUF_REQ = 1229,
+	CXIDV_TELEM_OXE_PRF_SET0_ST_READY = 1230,
+	CXIDV_TELEM_OXE_PRF_SET0_TS_SELECT = 1231,
+	CXIDV_TELEM_OXE_PRF_SET1_OCC_HIST_BIN0 = 1232,
+	CXIDV_TELEM_OXE_PRF_SET1_OCC_HIST_BIN1 = 1233,
+	CXIDV_TELEM_OXE_PRF_SET1_OCC_HIST_BIN2 = 1234,
+	CXIDV_TELEM_OXE_PRF_SET1_OCC_HIST_BIN3 = 1235,
+	CXIDV_TELEM_OXE_PRF_SET1_PKTBUF_NA = 1236,
+	CXIDV_TELEM_OXE_PRF_SET1_SMT_NA = 1237,
+	CXIDV_TELEM_OXE_PRF_SET1_SPT_NA = 1238,
+	CXIDV_TELEM_OXE_PRF_SET1_SRB_NA = 1239,
+	CXIDV_TELEM_OXE_PRF_SET1_ST_DMA_MDR = 1240,
+	CXIDV_TELEM_OXE_PRF_SET1_ST_DMA_UPD = 1241,
+	CXIDV_TELEM_OXE_PRF_SET1_ST_HEADER = 1242,
+	CXIDV_TELEM_OXE_PRF_SET1_ST_PCT_IDX_WAIT = 1243,
+	CXIDV_TELEM_OXE_PRF_SET1_ST_PKTBUF_GNT = 1244,
+	CXIDV_TELEM_OXE_PRF_SET1_ST_PKTBUF_REQ = 1245,
+	CXIDV_TELEM_OXE_PRF_SET1_ST_READY = 1246,
+	CXIDV_TELEM_OXE_PRF_SET1_TS_SELECT = 1247,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_0 = 1248,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_1 = 1249,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_2 = 1250,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_3 = 1251,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_4 = 1252,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_5 = 1253,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_6 = 1254,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_7 = 1255,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_8 = 1256,
+	CXIDV_TELEM_OXE_PTL_TX_GET_MSGS_TSC_9 = 1257,
+	CXIDV_TELEM_OXE_PTL_TX_MR_MSGS = 1258,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_0 = 1259,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_1 = 1260,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_2 = 1261,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_3 = 1262,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_4 = 1263,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_5 = 1264,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_6 = 1265,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_7 = 1266,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_8 = 1267,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_MSGS_TSC_9 = 1268,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_0 = 1269,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_1 = 1270,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_2 = 1271,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_3 = 1272,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_4 = 1273,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_5 = 1274,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_6 = 1275,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_7 = 1276,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_8 = 1277,
+	CXIDV_TELEM_OXE_PTL_TX_PUT_PKTS_TSC_9 = 1278,
+	CXIDV_TELEM_OXE_SMT_CDT_ERRS = 1279,
+	CXIDV_TELEM_OXE_SPT_CDT_ERRS = 1280,
+	CXIDV_TELEM_OXE_STALL_FGFC_BLK_0 = 1281,
+	CXIDV_TELEM_OXE_STALL_FGFC_BLK_1 = 1282,
+	CXIDV_TELEM_OXE_STALL_FGFC_BLK_2 = 1283,
+	CXIDV_TELEM_OXE_STALL_FGFC_BLK_3 = 1284,
+	CXIDV_TELEM_OXE_STALL_FGFC_CNTRL_0 = 1285,
+	CXIDV_TELEM_OXE_STALL_FGFC_CNTRL_1 = 1286,
+	CXIDV_TELEM_OXE_STALL_FGFC_CNTRL_2 = 1287,
+	CXIDV_TELEM_OXE_STALL_FGFC_CNTRL_3 = 1288,
+	CXIDV_TELEM_OXE_STALL_FGFC_END_0 = 1289,
+	CXIDV_TELEM_OXE_STALL_FGFC_END_1 = 1290,
+	CXIDV_TELEM_OXE_STALL_FGFC_END_2 = 1291,
+	CXIDV_TELEM_OXE_STALL_FGFC_END_3 = 1292,
+	CXIDV_TELEM_OXE_STALL_FGFC_START_0 = 1293,
+	CXIDV_TELEM_OXE_STALL_FGFC_START_1 = 1294,
+	CXIDV_TELEM_OXE_STALL_FGFC_START_2 = 1295,
+	CXIDV_TELEM_OXE_STALL_FGFC_START_3 = 1296,
+	CXIDV_TELEM_OXE_STALL_HDR_ARB = 1297,
+	CXIDV_TELEM_OXE_STALL_IDC_CMD_NO_DEQ = 1298,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_0 = 1299,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_1 = 1300,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_2 = 1301,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_3 = 1302,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_4 = 1303,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_5 = 1304,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_6 = 1305,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_7 = 1306,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_8 = 1307,
+	CXIDV_TELEM_OXE_STALL_IDC_NO_BUFF_BC_9 = 1308,
+	CXIDV_TELEM_OXE_STALL_IOI_LAST_ORDERED = 1309,
+	CXIDV_TELEM_OXE_STALL_NON_IDC_CMD_NO_DEQ = 1310,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_0 = 1311,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_1 = 1312,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_2 = 1313,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_3 = 1314,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_4 = 1315,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_5 = 1316,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_6 = 1317,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_7 = 1318,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_8 = 1319,
+	CXIDV_TELEM_OXE_STALL_PBUF_BC_9 = 1320,
+	CXIDV_TELEM_OXE_STALL_PCIE_SCOREBOARD = 1321,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_0 = 1322,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_1 = 1323,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_2 = 1324,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_3 = 1325,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_4 = 1326,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_5 = 1327,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_6 = 1328,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_7 = 1329,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_8 = 1330,
+	CXIDV_TELEM_OXE_STALL_PCT_BC_9 = 1331,
+	CXIDV_TELEM_OXE_STALL_STFWD_EOP = 1332,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_0 = 1333,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_1 = 1334,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_2 = 1335,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_3 = 1336,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_4 = 1337,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_5 = 1338,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_6 = 1339,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_7 = 1340,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_8 = 1341,
+	CXIDV_TELEM_OXE_STALL_TS_NO_IN_CRD_TSC_9 = 1342,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_0 = 1343,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_1 = 1344,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_2 = 1345,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_3 = 1346,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_4 = 1347,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_5 = 1348,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_6 = 1349,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_7 = 1350,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_8 = 1351,
+	CXIDV_TELEM_OXE_STALL_TS_NO_OUT_CRD_TSC_9 = 1352,
+	CXIDV_TELEM_OXE_STALL_WITH_NO_ATU_TAG = 1353,
+	CXIDV_TELEM_OXE_STALL_WITH_NO_PCI_TAG = 1354,
+	CXIDV_TELEM_OXE_STALL_WR_CONFLICT_PKT_BUFF_BNK_0 = 1355,
+	CXIDV_TELEM_OXE_STALL_WR_CONFLICT_PKT_BUFF_BNK_1 = 1356,
+	CXIDV_TELEM_OXE_STALL_WR_CONFLICT_PKT_BUFF_BNK_2 = 1357,
+	CXIDV_TELEM_OXE_STALL_WR_CONFLICT_PKT_BUFF_BNK_3 = 1358,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_0 = 1359,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_1 = 1360,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_2 = 1361,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_3 = 1362,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_4 = 1363,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_5 = 1364,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_6 = 1365,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_7 = 1366,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_8 = 1367,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_IDC_SHARED_9 = 1368,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_0 = 1369,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_1 = 1370,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_2 = 1371,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_3 = 1372,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_4 = 1373,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_5 = 1374,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_6 = 1375,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_7 = 1376,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_8 = 1377,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_RESERVED_9 = 1378,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_0 = 1379,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_1 = 1380,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_2 = 1381,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_3 = 1382,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_4 = 1383,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_5 = 1384,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_6 = 1385,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_7 = 1386,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_8 = 1387,
+	CXIDV_TELEM_OXE_STS_BC_OCC_BC_SHARED_9 = 1388,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_0 = 1389,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_1 = 1390,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_2 = 1391,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_3 = 1392,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_4 = 1393,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_5 = 1394,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_6 = 1395,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_7 = 1396,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_8 = 1397,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_9 = 1398,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_10 = 1399,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_11 = 1400,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_12 = 1401,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_13 = 1402,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_14 = 1403,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_15 = 1404,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_16 = 1405,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_17 = 1406,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_18 = 1407,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_19 = 1408,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_20 = 1409,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_21 = 1410,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_22 = 1411,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_23 = 1412,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_24 = 1413,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_25 = 1414,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_26 = 1415,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_27 = 1416,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_28 = 1417,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_29 = 1418,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_30 = 1419,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_31 = 1420,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_32 = 1421,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_33 = 1422,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_34 = 1423,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_35 = 1424,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_36 = 1425,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_37 = 1426,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_38 = 1427,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_39 = 1428,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_40 = 1429,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_41 = 1430,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_42 = 1431,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_43 = 1432,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_44 = 1433,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_45 = 1434,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_46 = 1435,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_47 = 1436,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_48 = 1437,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_49 = 1438,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_50 = 1439,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_51 = 1440,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_52 = 1441,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_53 = 1442,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_54 = 1443,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_55 = 1444,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_56 = 1445,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_57 = 1446,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_58 = 1447,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_59 = 1448,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_60 = 1449,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_61 = 1450,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_62 = 1451,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_63 = 1452,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_64 = 1453,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_65 = 1454,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_66 = 1455,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_67 = 1456,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_68 = 1457,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_69 = 1458,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_70 = 1459,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_71 = 1460,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_72 = 1461,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_73 = 1462,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_74 = 1463,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_75 = 1464,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_76 = 1465,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_77 = 1466,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_78 = 1467,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_79 = 1468,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_80 = 1469,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_81 = 1470,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_82 = 1471,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_83 = 1472,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_84 = 1473,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_85 = 1474,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_86 = 1475,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_87 = 1476,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_88 = 1477,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_89 = 1478,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_90 = 1479,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_91 = 1480,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_92 = 1481,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_93 = 1482,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_94 = 1483,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_IDC_CELL_COUNT_95 = 1484,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_0 = 1485,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_1 = 1486,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_2 = 1487,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_3 = 1488,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_4 = 1489,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_5 = 1490,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_6 = 1491,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_7 = 1492,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_8 = 1493,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_9 = 1494,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_10 = 1495,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_11 = 1496,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_12 = 1497,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_13 = 1498,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_14 = 1499,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_15 = 1500,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_16 = 1501,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_17 = 1502,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_18 = 1503,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_19 = 1504,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_20 = 1505,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_21 = 1506,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_22 = 1507,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_23 = 1508,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_24 = 1509,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_25 = 1510,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_26 = 1511,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_27 = 1512,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_28 = 1513,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_29 = 1514,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_30 = 1515,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_31 = 1516,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_32 = 1517,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_33 = 1518,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_34 = 1519,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_35 = 1520,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_36 = 1521,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_37 = 1522,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_38 = 1523,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_39 = 1524,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_40 = 1525,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_41 = 1526,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_42 = 1527,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_43 = 1528,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_44 = 1529,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_45 = 1530,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_46 = 1531,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_47 = 1532,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_48 = 1533,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_49 = 1534,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_50 = 1535,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_51 = 1536,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_52 = 1537,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_53 = 1538,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_54 = 1539,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_55 = 1540,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_56 = 1541,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_57 = 1542,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_58 = 1543,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_59 = 1544,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_60 = 1545,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_61 = 1546,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_62 = 1547,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_63 = 1548,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_64 = 1549,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_65 = 1550,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_66 = 1551,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_67 = 1552,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_68 = 1553,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_69 = 1554,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_70 = 1555,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_71 = 1556,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_72 = 1557,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_73 = 1558,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_74 = 1559,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_75 = 1560,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_76 = 1561,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_77 = 1562,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_78 = 1563,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_79 = 1564,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_80 = 1565,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_81 = 1566,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_82 = 1567,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_83 = 1568,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_84 = 1569,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_85 = 1570,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_86 = 1571,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_87 = 1572,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_88 = 1573,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_89 = 1574,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_90 = 1575,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_91 = 1576,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_92 = 1577,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_93 = 1578,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_94 = 1579,
+	CXIDV_TELEM_OXE_STS_MCU_OCC_MCU_CELL_COUNT_95 = 1580,
+	CXIDV_TELEM_PARBS_RARB_ATU_COMPLETION_PKTS = 1581,
+	CXIDV_TELEM_PARBS_RARB_ATU_POSTED_PKTS = 1582,
+	CXIDV_TELEM_PARBS_RARB_CQ_COMPLETION_PKTS = 1583,
+	CXIDV_TELEM_PARBS_RARB_CQ_POSTED_PKTS = 1584,
+	CXIDV_TELEM_PARBS_RARB_EE_POSTED_PKTS = 1585,
+	CXIDV_TELEM_PARBS_RARB_IXE_COMPLETION_PKTS = 1586,
+	CXIDV_TELEM_PARBS_RARB_IXE_POSTED_PKTS = 1587,
+	CXIDV_TELEM_PARBS_RARB_OXE_COMPLETION_PKTS = 1588,
+	CXIDV_TELEM_PARBS_RARB_PI_COMPLETION_PKTS = 1589,
+	CXIDV_TELEM_PARBS_RARB_PI_MBE_CNT = 1590,
+	CXIDV_TELEM_PARBS_RARB_PI_POSTED_PKTS = 1591,
+	CXIDV_TELEM_PARBS_RARB_PI_SBE_CNT = 1592,
+	CXIDV_TELEM_PARBS_STS_CREDITS_IN_USE_TARB_PI_NON_POSTED_CREDITS = 1593,
+	CXIDV_TELEM_PARBS_STS_CREDITS_IN_USE_TARB_PI_POSTED_CREDITS = 1594,
+	CXIDV_TELEM_PARBS_TARB_ATU_MBE_CNT = 1595,
+	CXIDV_TELEM_PARBS_TARB_ATU_NON_POSTED_FIFO_MBE = 1596,
+	CXIDV_TELEM_PARBS_TARB_ATU_NON_POSTED_FIFO_SBE = 1597,
+	CXIDV_TELEM_PARBS_TARB_ATU_NON_POSTED_PKTS = 1598,
+	CXIDV_TELEM_PARBS_TARB_ATU_POSTED_FIFO_MBE = 1599,
+	CXIDV_TELEM_PARBS_TARB_ATU_POSTED_FIFO_SBE = 1600,
+	CXIDV_TELEM_PARBS_TARB_ATU_POSTED_PKTS = 1601,
+	CXIDV_TELEM_PARBS_TARB_ATU_SBE_CNT = 1602,
+	CXIDV_TELEM_PARBS_TARB_CQ_MBE_CNT = 1603,
+	CXIDV_TELEM_PARBS_TARB_CQ_NON_POSTED_FIFO_MBE = 1604,
+	CXIDV_TELEM_PARBS_TARB_CQ_NON_POSTED_FIFO_SBE = 1605,
+	CXIDV_TELEM_PARBS_TARB_CQ_NON_POSTED_PKTS = 1606,
+	CXIDV_TELEM_PARBS_TARB_CQ_POSTED_FIFO_MBE = 1607,
+	CXIDV_TELEM_PARBS_TARB_CQ_POSTED_FIFO_SBE = 1608,
+	CXIDV_TELEM_PARBS_TARB_CQ_POSTED_PKTS = 1609,
+	CXIDV_TELEM_PARBS_TARB_CQ_SBE_CNT = 1610,
+	CXIDV_TELEM_PARBS_TARB_EE_MBE_CNT = 1611,
+	CXIDV_TELEM_PARBS_TARB_EE_POSTED_FIFO_MBE = 1612,
+	CXIDV_TELEM_PARBS_TARB_EE_POSTED_FIFO_SBE = 1613,
+	CXIDV_TELEM_PARBS_TARB_EE_POSTED_PKTS = 1614,
+	CXIDV_TELEM_PARBS_TARB_EE_SBE_CNT = 1615,
+	CXIDV_TELEM_PARBS_TARB_IXE_MBE_CNT = 1616,
+	CXIDV_TELEM_PARBS_TARB_IXE_NON_POSTED_FIFO_MBE = 1617,
+	CXIDV_TELEM_PARBS_TARB_IXE_NON_POSTED_FIFO_SBE = 1618,
+	CXIDV_TELEM_PARBS_TARB_IXE_NON_POSTED_PKTS = 1619,
+	CXIDV_TELEM_PARBS_TARB_IXE_POSTED_FIFO_MBE = 1620,
+	CXIDV_TELEM_PARBS_TARB_IXE_POSTED_FIFO_SBE = 1621,
+	CXIDV_TELEM_PARBS_TARB_IXE_POSTED_PKTS = 1622,
+	CXIDV_TELEM_PARBS_TARB_IXE_SBE_CNT = 1623,
+	CXIDV_TELEM_PARBS_TARB_OXE_MBE_CNT = 1624,
+	CXIDV_TELEM_PARBS_TARB_OXE_NON_POSTED_FIFO_MBE = 1625,
+	CXIDV_TELEM_PARBS_TARB_OXE_NON_POSTED_FIFO_SBE = 1626,
+	CXIDV_TELEM_PARBS_TARB_OXE_NON_POSTED_PKTS = 1627,
+	CXIDV_TELEM_PARBS_TARB_OXE_SBE_CNT = 1628,
+	CXIDV_TELEM_PARBS_TARB_PI_NON_POSTED_BLOCKED_CNT = 1629,
+	CXIDV_TELEM_PARBS_TARB_PI_NON_POSTED_PKTS = 1630,
+	CXIDV_TELEM_PARBS_TARB_PI_POSTED_BLOCKED_CNT = 1631,
+	CXIDV_TELEM_PARBS_TARB_PI_POSTED_PKTS = 1632,
+	CXIDV_TELEM_PCT_ACCEL_CLOSE = 1633,
+	CXIDV_TELEM_PCT_BAD_SEQ_NACKS = 1634,
+	CXIDV_TELEM_PCT_CLEAR_CLOSE_DROP = 1635,
+	CXIDV_TELEM_PCT_CLEAR_SENT = 1636,
+	CXIDV_TELEM_PCT_CLOSE_RSP_DROPS = 1637,
+	CXIDV_TELEM_PCT_CLOSE_SENT = 1638,
+	CXIDV_TELEM_PCT_CLR_CLS_STALLS = 1639,
+	CXIDV_TELEM_PCT_CLS_REQ_BAD_SEQNO_DROPS = 1640,
+	CXIDV_TELEM_PCT_CLS_REQ_MISS_TCT = 1641,
+	CXIDV_TELEM_PCT_CONN_SCT_OPEN = 1642,
+	CXIDV_TELEM_PCT_CONN_TCT_OPEN = 1643,
+	CXIDV_TELEM_PCT_ERR_NO_MATCHING_MST = 1644,
+	CXIDV_TELEM_PCT_ERR_NO_MATCHING_TRS = 1645,
+	CXIDV_TELEM_PCT_ETH_PACKETS = 1646,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_0 = 1647,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_1 = 1648,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_2 = 1649,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_3 = 1650,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_4 = 1651,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_5 = 1652,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_6 = 1653,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_7 = 1654,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_8 = 1655,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_9 = 1656,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_10 = 1657,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_11 = 1658,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_12 = 1659,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_13 = 1660,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_14 = 1661,
+	CXIDV_TELEM_PCT_HOST_ACCESS_LATENCY_15 = 1662,
+	CXIDV_TELEM_PCT_HRP_RESPONSES_RECEIVED = 1663,
+	CXIDV_TELEM_PCT_HRP_RSP_DISCARD_RECEIVED = 1664,
+	CXIDV_TELEM_PCT_HRP_RSP_ERR_RECEIVED = 1665,
+	CXIDV_TELEM_PCT_MEM_COR_ERR_CNTR = 1666,
+	CXIDV_TELEM_PCT_MEM_UCOR_ERR_CNTR = 1667,
+	CXIDV_TELEM_PCT_MST_HIT_ON_SOM = 1668,
+	CXIDV_TELEM_PCT_NO_MATCHING_TCT = 1669,
+	CXIDV_TELEM_PCT_NO_MST_NACKS = 1670,
+	CXIDV_TELEM_PCT_NO_TCT_NACKS = 1671,
+	CXIDV_TELEM_PCT_NO_TRS_NACKS = 1672,
+	CXIDV_TELEM_PCT_OPTIP_PACKETS = 1673,
+	CXIDV_TELEM_PCT_PCT_CQ_NOTIFICATIONS = 1674,
+	CXIDV_TELEM_PCT_PCT_CQ_STALLS = 1675,
+	CXIDV_TELEM_PCT_PCT_EE_EVENTS = 1676,
+	CXIDV_TELEM_PCT_PCT_EE_STALLS = 1677,
+	CXIDV_TELEM_PCT_PCT_HNI_FLITS = 1678,
+	CXIDV_TELEM_PCT_PCT_HNI_STALLS = 1679,
+	CXIDV_TELEM_PCT_PCT_MST_CMD0 = 1680,
+	CXIDV_TELEM_PCT_PCT_MST_CMD1 = 1681,
+	CXIDV_TELEM_PCT_PCT_MST_STALLS0 = 1682,
+	CXIDV_TELEM_PCT_PCT_MST_STALLS1 = 1683,
+	CXIDV_TELEM_PCT_PRF_MST_STATUS_MAX_MST_IN_USE = 1684,
+	CXIDV_TELEM_PCT_PRF_MST_STATUS_MST_IN_USE = 1685,
+	CXIDV_TELEM_PCT_PRF_SCT_STATUS_MAX_SCT_IN_USE = 1686,
+	CXIDV_TELEM_PCT_PRF_SCT_STATUS_SCT_IN_USE = 1687,
+	CXIDV_TELEM_PCT_PRF_SMT_STATUS_MAX_SMT_IN_USE = 1688,
+	CXIDV_TELEM_PCT_PRF_SMT_STATUS_SMT_IN_USE = 1689,
+	CXIDV_TELEM_PCT_PRF_SPT_STATUS_MAX_SPT_IN_USE = 1690,
+	CXIDV_TELEM_PCT_PRF_SPT_STATUS_SPT_IN_USE = 1691,
+	CXIDV_TELEM_PCT_PRF_SRB_STATUS_MAX_SRB_IN_USE = 1692,
+	CXIDV_TELEM_PCT_PRF_SRB_STATUS_SRB_IN_USE = 1693,
+	CXIDV_TELEM_PCT_PRF_TCT_STATUS_MAX_TCT_IN_USE = 1694,
+	CXIDV_TELEM_PCT_PRF_TCT_STATUS_TCT_IN_USE = 1695,
+	CXIDV_TELEM_PCT_PRF_TRS_STATUS_MAX_TRS_IN_USE = 1696,
+	CXIDV_TELEM_PCT_PRF_TRS_STATUS_TRS_IN_USE = 1697,
+	CXIDV_TELEM_PCT_PTLS_RESPONSE = 1698,
+	CXIDV_TELEM_PCT_REQ_BLOCKED_CLEARING = 1699,
+	CXIDV_TELEM_PCT_REQ_BLOCKED_CLOSING = 1700,
+	CXIDV_TELEM_PCT_REQ_BLOCKED_RETRY = 1701,
+	CXIDV_TELEM_PCT_REQ_NO_RESPONSE = 1702,
+	CXIDV_TELEM_PCT_REQ_ORDERED = 1703,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_0 = 1704,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_1 = 1705,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_2 = 1706,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_3 = 1707,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_4 = 1708,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_5 = 1709,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_6 = 1710,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_7 = 1711,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_8 = 1712,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_9 = 1713,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_10 = 1714,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_11 = 1715,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_12 = 1716,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_13 = 1717,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_14 = 1718,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_15 = 1719,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_16 = 1720,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_17 = 1721,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_18 = 1722,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_19 = 1723,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_20 = 1724,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_21 = 1725,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_22 = 1726,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_23 = 1727,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_24 = 1728,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_25 = 1729,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_26 = 1730,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_27 = 1731,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_28 = 1732,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_29 = 1733,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_30 = 1734,
+	CXIDV_TELEM_PCT_REQ_RSP_LATENCY_31 = 1735,
+	CXIDV_TELEM_PCT_REQ_SRC_ERROR = 1736,
+	CXIDV_TELEM_PCT_REQ_TCT_TMOUT_DROPS = 1737,
+	CXIDV_TELEM_PCT_REQ_UNORDERED = 1738,
+	CXIDV_TELEM_PCT_RESOURCE_BUSY = 1739,
+	CXIDV_TELEM_PCT_RESPONSES_RECEIVED = 1740,
+	CXIDV_TELEM_PCT_RETRY_MST_GET = 1741,
+	CXIDV_TELEM_PCT_RETRY_SRB_REQUESTS = 1742,
+	CXIDV_TELEM_PCT_RETRY_TRS_PUT = 1743,
+	CXIDV_TELEM_PCT_RSP_DROPPED_CLS_TRY = 1744,
+	CXIDV_TELEM_PCT_RSP_DROPPED_INACTIVE = 1745,
+	CXIDV_TELEM_PCT_RSP_DROPPED_TIMEOUT = 1746,
+	CXIDV_TELEM_PCT_RSP_DROPPED_TRY = 1747,
+	CXIDV_TELEM_PCT_RSP_ERR_RCVD = 1748,
+	CXIDV_TELEM_PCT_SCT_STALL_STATE = 1749,
+	CXIDV_TELEM_PCT_SCT_TIMEOUTS = 1750,
+	CXIDV_TELEM_PCT_SPT_TIMEOUTS = 1751,
+	CXIDV_TELEM_PCT_TCT_TIMEOUTS = 1752,
+	CXIDV_TELEM_PCT_TGT_CLS_ABORT = 1753,
+	CXIDV_TELEM_PCT_TRS_HIT_ON_REQ = 1754,
+	CXIDV_TELEM_PCT_TRS_REPLAY_PEND_DROPS = 1755,
+	CXIDV_TELEM_PCT_TRS_RSP_NACK_DROPS = 1756,
+	CXIDV_TELEM_PI_DMAC_AXI_RD_REQUESTS = 1757,
+	CXIDV_TELEM_PI_DMAC_AXI_RD_RSP_DECERRS = 1758,
+	CXIDV_TELEM_PI_DMAC_AXI_RD_RSP_PARERRS = 1759,
+	CXIDV_TELEM_PI_DMAC_AXI_RD_RSP_SLVERRS = 1760,
+	CXIDV_TELEM_PI_DMAC_CE_MWR_TLPS = 1761,
+	CXIDV_TELEM_PI_DMAC_DESC_COR_ERRORS = 1762,
+	CXIDV_TELEM_PI_DMAC_DESC_UCOR_ERRORS = 1763,
+	CXIDV_TELEM_PI_DMAC_IRQS = 1764,
+	CXIDV_TELEM_PI_DMAC_PAYLOAD_MWR_TLPS = 1765,
+	CXIDV_TELEM_PI_IPD_CFG_EVENT_CNTS_OVF_CNT = 1766,
+	CXIDV_TELEM_PI_IPD_DBIC_DBI_ACKS = 1767,
+	CXIDV_TELEM_PI_IPD_DBIC_DBI_REQUESTS = 1768,
+	CXIDV_TELEM_PI_IPD_DMAC_P_FIFO_COR_ERRORS = 1769,
+	CXIDV_TELEM_PI_IPD_DMAC_P_FIFO_UCOR_ERRORS = 1770,
+	CXIDV_TELEM_PI_IPD_IPD_TRIGGER_EVENTS_0 = 1771,
+	CXIDV_TELEM_PI_IPD_IPD_TRIGGER_EVENTS_1 = 1772,
+	CXIDV_TELEM_PI_IPD_MSIXC_IB_IRQ_PBAS = 1773,
+	CXIDV_TELEM_PI_IPD_MSIXC_IB_IRQS_DISCARDED = 1774,
+	CXIDV_TELEM_PI_IPD_MSIXC_IB_IRQS_SENT = 1775,
+	CXIDV_TELEM_PI_IPD_MSIXC_IB_LEGACY_IRQS_SENT = 1776,
+	CXIDV_TELEM_PI_IPD_MSIXC_OOB_IRQ_PBAS = 1777,
+	CXIDV_TELEM_PI_IPD_MSIXC_OOB_IRQS_DISCARDED = 1778,
+	CXIDV_TELEM_PI_IPD_MSIXC_OOB_IRQS_SENT = 1779,
+	CXIDV_TELEM_PI_IPD_MSIXC_OOB_LEGACY_IRQS_SENT = 1780,
+	CXIDV_TELEM_PI_IPD_MSIXC_PBA_COR_ERRORS = 1781,
+	CXIDV_TELEM_PI_IPD_MSIXC_PBA_UCOR_ERRORS = 1782,
+	CXIDV_TELEM_PI_IPD_MSIXC_PTI_FIFO_COR_ERRORS = 1783,
+	CXIDV_TELEM_PI_IPD_MSIXC_PTI_FIFO_UCOR_ERRORS = 1784,
+	CXIDV_TELEM_PI_IPD_MSIXC_TABLE_COR_ERRORS = 1785,
+	CXIDV_TELEM_PI_IPD_MSIXC_TABLE_UCOR_ERRORS = 1786,
+	CXIDV_TELEM_PI_IPD_PRI_RBYP_DATA_PARITY_ERRORS = 1787,
+	CXIDV_TELEM_PI_IPD_PRI_RBYP_HDR_PARITY_ERRORS = 1788,
+	CXIDV_TELEM_PI_IPD_PRI_RBYP_TLPS = 1789,
+	CXIDV_TELEM_PI_IPD_PRI_RBYP_TLPS_ABORTED = 1790,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_BLOCKED_ON_MB = 1791,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_BLOCKED_ON_RARB = 1792,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_DATA_PARITY_ERRORS = 1793,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_HDR_PARITY_ERRORS = 1794,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_MRD_TLPS = 1795,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_MSG_TLPS = 1796,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_MSGD_TLPS = 1797,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_MWR_TLPS = 1798,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_TLPS = 1799,
+	CXIDV_TELEM_PI_IPD_PRI_RTRGT_TLPS_ABORTED = 1800,
+	CXIDV_TELEM_PI_IPD_PTI_DBG_BLOCKED_ON_NPH_CRD = 1801,
+	CXIDV_TELEM_PI_IPD_PTI_DBG_BLOCKED_ON_PD_CRD = 1802,
+	CXIDV_TELEM_PI_IPD_PTI_DBG_BLOCKED_ON_PH_CRD = 1803,
+	CXIDV_TELEM_PI_IPD_PTI_DBG_BLOCKED_ON_TAG = 1804,
+	CXIDV_TELEM_PI_IPD_PTI_DBG_XALI_NON_POSTED_TLPS = 1805,
+	CXIDV_TELEM_PI_IPD_PTI_DBG_XALI_POSTED_TLPS = 1806,
+	CXIDV_TELEM_PI_IPD_PTI_DMAC_BLOCKED_ON_PD_CRD = 1807,
+	CXIDV_TELEM_PI_IPD_PTI_DMAC_BLOCKED_ON_PH_CRD = 1808,
+	CXIDV_TELEM_PI_IPD_PTI_DMAC_XALI_POSTED_TLPS = 1809,
+	CXIDV_TELEM_PI_IPD_PTI_MSIXC_BLOCKED_ON_PD_CRD = 1810,
+	CXIDV_TELEM_PI_IPD_PTI_MSIXC_BLOCKED_ON_PH_CRD = 1811,
+	CXIDV_TELEM_PI_IPD_PTI_MSIXC_FIFO_COR_ERRORS = 1812,
+	CXIDV_TELEM_PI_IPD_PTI_MSIXC_FIFO_UCOR_ERRORS = 1813,
+	CXIDV_TELEM_PI_IPD_PTI_MSIXC_XALI_POSTED_TLPS = 1814,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_BLOCKED_ON_NPD_CRD = 1815,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_BLOCKED_ON_NPH_CRD = 1816,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_BLOCKED_ON_PD_CRD = 1817,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_BLOCKED_ON_PH_CRD = 1818,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_BLOCKED_ON_TAG = 1819,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_CMPL_TO = 1820,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_CMPL_TO_FIFO_COR_ERRORS = 1821,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_CMPL_TO_FIFO_UCOR_ERRORS = 1822,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_NP_FIFO_COR_ERRORS = 1823,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_NP_FIFO_UCOR_ERRORS = 1824,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_P_FIFO_COR_ERRORS = 1825,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_P_FIFO_UCOR_ERRORS = 1826,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_XALI_NON_POSTED_TLPS = 1827,
+	CXIDV_TELEM_PI_IPD_PTI_TARB_XALI_POSTED_TLPS = 1828,
+	CXIDV_TELEM_PI_PRI_MB_AXI_RD_REQUESTS = 1829,
+	CXIDV_TELEM_PI_PRI_MB_AXI_RD_RSP_DECERRS = 1830,
+	CXIDV_TELEM_PI_PRI_MB_AXI_RD_RSP_PARERRS = 1831,
+	CXIDV_TELEM_PI_PRI_MB_AXI_RD_RSP_SLVERRS = 1832,
+	CXIDV_TELEM_PI_PRI_MB_AXI_WR_REQUESTS = 1833,
+	CXIDV_TELEM_PI_PRI_MB_AXI_WR_RSP_DECERRS = 1834,
+	CXIDV_TELEM_PI_PRI_MB_AXI_WR_RSP_SLVERRS = 1835,
+	CXIDV_TELEM_PI_PRI_MB_RTRGT_FIFO_COR_ERRORS = 1836,
+	CXIDV_TELEM_PI_PRI_MB_RTRGT_FIFO_UCOR_ERRORS = 1837,
+	CXIDV_TELEM_PI_PRI_MB_RTRGT_MRD_TLPS = 1838,
+	CXIDV_TELEM_PI_PRI_MB_RTRGT_MWR_TLPS = 1839,
+	CXIDV_TELEM_PI_PRI_MB_RTRGT_NON_POSTED_TLP_DISCARDS = 1840,
+	CXIDV_TELEM_PI_PRI_MB_RTRGT_POSTED_TLP_DISCARDS = 1841,
+	CXIDV_TELEM_PI_PRI_MB_RTRGT_POSTED_TLP_PARTIAL_DISCARDS = 1842,
+	CXIDV_TELEM_PI_PRI_MB_RTRGT_TLP_DISCARDS = 1843,
+	CXIDV_TELEM_PI_PRI_MB_RTRGT_TLPS = 1844,
+	CXIDV_TELEM_PI_PRI_MB_XALI_CMPL_CA_TLPS = 1845,
+	CXIDV_TELEM_PI_PRI_MB_XALI_CMPL_TLPS = 1846,
+	CXIDV_TELEM_PI_PRI_MB_XALI_CMPL_UR_TLPS = 1847,
+	CXIDV_TELEM_PI_PRI_RARB_RBYP_FIFO_COR_ERRORS = 1848,
+	CXIDV_TELEM_PI_PRI_RARB_RBYP_FIFO_UCOR_ERRORS = 1849,
+	CXIDV_TELEM_PI_PRI_RARB_RBYP_TLP_DISCARDS = 1850,
+	CXIDV_TELEM_PI_PRI_RARB_RBYP_TLPS = 1851,
+	CXIDV_TELEM_PI_PRI_RARB_RTRGT_FIFO_COR_ERRORS = 1852,
+	CXIDV_TELEM_PI_PRI_RARB_RTRGT_FIFO_UCOR_ERRORS = 1853,
+	CXIDV_TELEM_PI_PRI_RARB_RTRGT_MSG_TLPS = 1854,
+	CXIDV_TELEM_PI_PRI_RARB_RTRGT_MSGD_TLPS = 1855,
+	CXIDV_TELEM_PI_PRI_RARB_RTRGT_MWR_TLPS = 1856,
+	CXIDV_TELEM_PI_PRI_RARB_RTRGT_TLP_DISCARDS = 1857,
+	CXIDV_TELEM_PI_PRI_RARB_RTRGT_TLPS = 1858,
+	CXIDV_TELEM_PI_PRI_RARB_SRIOVT_COR_ERRORS = 1859,
+	CXIDV_TELEM_PI_PRI_RARB_SRIOVT_UCOR_ERRORS = 1860,
+	CXIDV_TELEM_PI_PTI_TARB_ACXT_COR_ERRORS = 1861,
+	CXIDV_TELEM_PI_PTI_TARB_ACXT_UCOR_ERRORS = 1862,
+	CXIDV_TELEM_PI_PTI_TARB_AMO_PKTS = 1863,
+	CXIDV_TELEM_PI_PTI_TARB_DATA_COR_ERRORS = 1864,
+	CXIDV_TELEM_PI_PTI_TARB_DATA_UCOR_ERROR = 1865,
+	CXIDV_TELEM_PI_PTI_TARB_FETCHING_AMO_PKTS = 1866,
+	CXIDV_TELEM_PI_PTI_TARB_FLUSH_PKTS = 1867,
+	CXIDV_TELEM_PI_PTI_TARB_HDR_COR_ERRORS = 1868,
+	CXIDV_TELEM_PI_PTI_TARB_HDR_UCOR_ERRORS = 1869,
+	CXIDV_TELEM_PI_PTI_TARB_INV_RSP_PKTS = 1870,
+	CXIDV_TELEM_PI_PTI_TARB_IRQ_PKTS = 1871,
+	CXIDV_TELEM_PI_PTI_TARB_MRD_PKTS = 1872,
+	CXIDV_TELEM_PI_PTI_TARB_MWR_PKTS = 1873,
+	CXIDV_TELEM_PI_PTI_TARB_PG_REQ_PKTS = 1874,
+	CXIDV_TELEM_PI_PTI_TARB_PKT_DISCARDS = 1875,
+	CXIDV_TELEM_PI_PTI_TARB_PKTS = 1876,
+	CXIDV_TELEM_PI_PTI_TARB_RARB_CA_PKTS = 1877,
+	CXIDV_TELEM_PI_PTI_TARB_TRANSLATION_PKTS = 1878,
+	CXIDV_TELEM_RMU_ENET_FRAME_REJECTED_CNTR = 1879,
+	CXIDV_TELEM_RMU_ENET_PTLTE_SET_CTRL_ERR_CNTR = 1880,
+	CXIDV_TELEM_RMU_ENET_SUCCESS_CNTR = 1881,
+	CXIDV_TELEM_RMU_MEM_COR_ERR_CNTR = 1882,
+	CXIDV_TELEM_RMU_MEM_UCOR_ERR_CNTR = 1883,
+	CXIDV_TELEM_RMU_PTL_INVLD_DFA_CNTR = 1884,
+	CXIDV_TELEM_RMU_PTL_INVLD_VNI_CNTR = 1885,
+	CXIDV_TELEM_RMU_PTL_NO_PTLTE_CNTR = 1886,
+	CXIDV_TELEM_RMU_PTL_SUCCESS_CNTR = 1887,
+	CXIDV_TELEM_TOU_CMD_FIFO_FULL_CYCLES = 1888,
+	CXIDV_TELEM_TOU_CQ_TOU_NUM_CMDS = 1889,
+	CXIDV_TELEM_TOU_CQ_TOU_NUM_STALLS = 1890,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_0 = 1891,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_1 = 1892,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_2 = 1893,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_3 = 1894,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_4 = 1895,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_5 = 1896,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_6 = 1897,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_7 = 1898,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_8 = 1899,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_9 = 1900,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_10 = 1901,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_11 = 1902,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_12 = 1903,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_13 = 1904,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_14 = 1905,
+	CXIDV_TELEM_TOU_CT_CMD_COUNTS_15 = 1906,
+	CXIDV_TELEM_TOU_FAIL_CNTR = 1907,
+	CXIDV_TELEM_TOU_LIST_REBUILD_CYCLES = 1908,
+	CXIDV_TELEM_TOU_NUM_CT_UPDATES = 1909,
+	CXIDV_TELEM_TOU_NUM_DOORBELL_WRITES = 1910,
+	CXIDV_TELEM_TOU_NUM_LIST_REBUILDS_0 = 1911,
+	CXIDV_TELEM_TOU_NUM_LIST_REBUILDS_1 = 1912,
+	CXIDV_TELEM_TOU_NUM_LIST_REBUILDS_2 = 1913,
+	CXIDV_TELEM_TOU_NUM_LIST_REBUILDS_3 = 1914,
+	CXIDV_TELEM_TOU_NUM_TRIG_CMDS_0 = 1915,
+	CXIDV_TELEM_TOU_NUM_TRIG_CMDS_1 = 1916,
+	CXIDV_TELEM_TOU_NUM_TRIG_CMDS_2 = 1917,
+	CXIDV_TELEM_TOU_NUM_TRIG_CMDS_3 = 1918,
+	CXIDV_TELEM_TOU_SUCCESS_CNTR = 1919,
+	CXIDV_TELEM_TOU_TOU_OXE_NUM_FLITS = 1920,
+	CXIDV_TELEM_TOU_TOU_OXE_NUM_IDLES = 1921,
+	CXIDV_TELEM_TOU_TOU_OXE_NUM_STALLS = 1922,
+	CXIDV_TELEM_COUNT = 1923,
+};
+
+/* Predefined groups of items */
+enum cxidv_telem_set {
+	CXIDV_TELEM_SET_ETHTOOL,
+	CXIDV_TELEM_SET_ATU,
+	CXIDV_TELEM_SET_CQ,
+	CXIDV_TELEM_SET_EE,
+	CXIDV_TELEM_SET_HNI,
+	CXIDV_TELEM_SET_IXE,
+	CXIDV_TELEM_SET_LPE,
+	CXIDV_TELEM_SET_MB,
+	CXIDV_TELEM_SET_MST,
+	CXIDV_TELEM_SET_OXE,
+	CXIDV_TELEM_SET_PARBS,
+	CXIDV_TELEM_SET_PCT,
+	CXIDV_TELEM_SET_PI,
+	CXIDV_TELEM_SET_RMU,
+	CXIDV_TELEM_SET_TOU,
+	CXIDV_TELEM_SET_COUNT,
+};
+
+/* Name of an item as the sysfs telemetry files had it, or NULL */
+const char *cxidv_telem_name(uint32_t item);
+
+/* Item number for a name, or -1 if there is no such item */
+int cxidv_telem_lookup(const char *name);
+
+/* Items of a predefined set. Returns 0, or an errno value. */
+int cxidv_telem_get_set(enum cxidv_telem_set set, const uint64_t **items, uint32_t *count);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

-- 
2.56.0