[PATCH v2 2/2] arm64: dts: qcom: lemans-sa8255p: add ethernet nodes
From: Bartosz Golaszewski
Date: Tue Nov 03 2026 - 07:34:02 EST
Add the ethernet nodes along with their serdes PHY nodes for the gearvm
variant of the lemans ride board. Enable scmi7 and scmi8 to serve the
EMACs.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/lemans-gearvm.dtsi | 30 ++++
arch/arm64/boot/dts/qcom/lemans-sa8255p-ride.dts | 207 +++++++++++++++++++++++
2 files changed, 237 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/lemans-gearvm.dtsi b/arch/arm64/boot/dts/qcom/lemans-gearvm.dtsi
index 91c97a55f2787406b104650956b9a511a6a34c23..96a54f32f0eeb16dbce9802e74eec82622ecd35f 100644
--- a/arch/arm64/boot/dts/qcom/lemans-gearvm.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans-gearvm.dtsi
@@ -58,6 +58,18 @@ &cpufreq_hw {
clock-names = "xo", "alternate";
};
+ðernet0 {
+ compatible = "qcom,sa8255p-ethqos";
+ phys = <&serdes0>;
+ phy-names = "serdes";
+};
+
+ðernet1 {
+ compatible = "qcom,sa8255p-ethqos";
+ phys = <&serdes1>;
+ phy-names = "serdes";
+};
+
&firmware {
scmi0: scmi-0 {
compatible = "qcom,scmi-smc";
@@ -3218,6 +3230,24 @@ &uart21 {
"perf";
};
+&soc {
+ serdes0: phy@8901000 {
+ compatible = "qcom,sa8255p-dwmac-sgmii-phy";
+ reg = <0x0 0x08901000 0x0 0xe10>;
+ #phy-cells = <0>;
+ power-domains = <&scmi7_dvfs 0>;
+ status = "disabled";
+ };
+
+ serdes1: phy@8902000 {
+ compatible = "qcom,sa8255p-dwmac-sgmii-phy";
+ reg = <0x0 0x08902000 0x0 0xe10>;
+ #phy-cells = <0>;
+ power-domains = <&scmi8_dvfs 0>;
+ status = "disabled";
+ };
+};
+
&ufs_mem_hc {
compatible = "qcom,sa8255p-ufshc";
power-domains = <&scmi3_pd 0>;
diff --git a/arch/arm64/boot/dts/qcom/lemans-sa8255p-ride.dts b/arch/arm64/boot/dts/qcom/lemans-sa8255p-ride.dts
index 6f19064997a4b50525fdf630307b843604368645..2b3c9e90802bf89b91354039f0e6a24941fc95d5 100644
--- a/arch/arm64/boot/dts/qcom/lemans-sa8255p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/lemans-sa8255p-ride.dts
@@ -14,6 +14,8 @@ / {
compatible = "qcom,sa8255p-ride", "qcom,sa8255p";
aliases {
+ ethernet0 = ðernet0;
+ ethernet1 = ðernet1;
serial0 = &uart10;
serial1 = &uart4;
};
@@ -101,6 +103,179 @@ trip1 {
};
};
+ðernet0 {
+ phy-handle = <&sgmii_phy0>;
+ phy-mode = "2500base-x";
+
+ pinctrl-0 = <ðernet0_default>;
+ pinctrl-names = "default";
+
+ snps,mtl-rx-config = <&mtl_rx_setup>;
+ snps,mtl-tx-config = <&mtl_tx_setup>;
+ snps,ps-speed = <2500>;
+
+ power-domains = <&scmi7_pd 0>, <&scmi7_pd 1>;
+ power-domain-names = "core", "mdio";
+
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sgmii_phy0: phy@8 {
+ compatible = "ethernet-phy-id31c3.1c33";
+ reg = <0x8>;
+ device_type = "ethernet-phy";
+ resets = <&scmi7_rst 0>;
+ reset-names = "phy";
+ reset-assert-us = <11000>;
+ reset-deassert-us = <70000>;
+ };
+
+ sgmii_phy1: phy@0 {
+ compatible = "ethernet-phy-id31c3.1c33";
+ reg = <0x0>;
+ device_type = "ethernet-phy";
+ resets = <&scmi8_rst 0>;
+ reset-names = "phy";
+ reset-assert-us = <11000>;
+ reset-deassert-us = <70000>;
+ };
+ };
+
+ mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <4>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ snps,route-up;
+ snps,priority = <0x1>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x1>;
+ snps,route-ptp;
+ };
+
+ queue2 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x2>;
+ snps,route-avcp;
+ };
+
+ queue3 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x3>;
+ snps,priority = <0xc>;
+ };
+ };
+
+ mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <4>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ };
+
+ queue2 {
+ snps,avb-algorithm;
+ snps,send_slope = <0x1000>;
+ snps,idle_slope = <0x1000>;
+ snps,high_credit = <0x3e800>;
+ snps,low_credit = <0xffc18000>;
+ };
+
+ queue3 {
+ snps,avb-algorithm;
+ snps,send_slope = <0x1000>;
+ snps,idle_slope = <0x1000>;
+ snps,high_credit = <0x3e800>;
+ snps,low_credit = <0xffc18000>;
+ };
+ };
+};
+
+ðernet1 {
+ phy-mode = "2500base-x";
+ phy-handle = <&sgmii_phy1>;
+
+ snps,mtl-rx-config = <&mtl_rx_setup1>;
+ snps,mtl-tx-config = <&mtl_tx_setup1>;
+ snps,ps-speed = <2500>;
+
+ power-domains = <&scmi8_pd 0>, <&scmi8_pd 1>;
+ power-domain-names = "core", "mdio";
+
+ status = "okay";
+
+ mtl_rx_setup1: rx-queues-config {
+ snps,rx-queues-to-use = <4>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ snps,route-up;
+ snps,priority = <0x1>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x1>;
+ snps,route-ptp;
+ };
+
+ queue2 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x2>;
+ snps,route-avcp;
+ };
+
+ queue3 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x3>;
+ snps,priority = <0xc>;
+ };
+ };
+
+ mtl_tx_setup1: tx-queues-config {
+ snps,tx-queues-to-use = <4>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ };
+
+ queue2 {
+ snps,avb-algorithm;
+ snps,send_slope = <0x1000>;
+ snps,idle_slope = <0x1000>;
+ snps,high_credit = <0x3e800>;
+ snps,low_credit = <0xffc18000>;
+ };
+
+ queue3 {
+ snps,avb-algorithm;
+ snps,send_slope = <0x1000>;
+ snps,idle_slope = <0x1000>;
+ snps,high_credit = <0x3e800>;
+ snps,low_credit = <0xffc18000>;
+ };
+ };
+};
+
&gpll0_board_clk {
clock-frequency = <300000000>;
};
@@ -145,6 +320,14 @@ &scmi6 {
status = "okay";
};
+&scmi7 {
+ status = "okay";
+};
+
+&scmi8 {
+ status = "okay";
+};
+
&scmi11 {
status = "okay";
};
@@ -162,6 +345,22 @@ &sleep_clk {
};
&tlmm {
+ ethernet0_default: ethernet0-default-state {
+ ethernet0_mdc: ethernet0-mdc-pins {
+ pins = "gpio8";
+ function = "emac0_mdc";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ ethernet0_mdio: ethernet0-mdio-pins {
+ pins = "gpio9";
+ function = "emac0_mdio";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+
pcie0_ep_clkreq_default: pcie0-ep-clkreq-default-state {
pins = "gpio1";
function = "pcie0_clkreq";
@@ -205,6 +404,14 @@ pcie1_ep_wake_default: pcie1-ep-wake-default-state {
};
};
+&serdes0 {
+ status = "okay";
+};
+
+&serdes1 {
+ status = "okay";
+};
+
&uart4 {
status = "okay";
};
--
2.47.3