Re: [PATCH 04/13] wifi: brcmfmac: Support newer PCIe core startup and interrupts

[Arend van Spriel]

On Fri, 25 Sep 2026 23:43:39 +1000, Michael Reeves <michael.reeves077@xxxxxxxxx> wrote:
> From: Hector Martin <marcan@xxxxxxxxx>
>
> Newer Broadcom chips, such as BCM4388, require changes to PCIe register
> access, watchdog reset, and RAM size detection. PCIe core revision 64
> and higher uses a different BAR0 register window. ChipCommon revision 65
> and higher requires a different watchdog reset sequence.
>
> Update register access and reset for these revisions. Decode the SYSMEM
> bank counts according to the core revision and exclude ROM banks from
> RAM size calculation. Disable all detected D11 cores during CA7 setup
> and select H2D doorbells based on the firmware DAR flag.
>
> In MSI mode, firmware can clear the mailbox interrupt status before the
> host reads it. Requiring a nonzero status can therefore discard valid
> interrupts. Process ring events without that requirement when MSI is
> enabled. Use release/acquire ordering on irq_ready to publish the
> initialized rings before the interrupt thread accesses them.
>

Acked-by: Arend van Spriel <arend.vanspriel@xxxxxxxxxxxx>

Regards,
Arend

> Signed-off-by: Hector Martin <marcan@xxxxxxxxx>
> Co-developed-by: Michael Reeves <michael.reeves077@xxxxxxxxx>
> Signed-off-by: Michael Reeves <michael.reeves077@xxxxxxxxx>
> ---
>  .../wireless/broadcom/brcm80211/brcmfmac/chip.c    |  35 +++-
>  .../wireless/broadcom/brcm80211/brcmfmac/pcie.c    | 197 ++++++++++++++++-----
>  .../broadcom/brcm80211/include/chipcommon.h        |   5 +
>  3 files changed, 183 insertions(+), 54 deletions(-)