[PATCH 0/4] clk/drm: renesas: Improve RZ/V2H(P) MIPI DSI PLL parameter selection

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Hi all,

On RZ/V2H(P) and RZ/V2N the DSI HS clock is derived from the pixel clock
produced by the CPG PLLDSI and its divider (HS clock = pixel clock *
bpp / lanes), and the PLL in the DSI block has to reproduce it to within
0.5 Hz. A display mode is usable only if a single set of CPG parameters
satisfies both the CPG and the DSI PLL constraints, but the two were
checked one after the other instead of together:

 - Mode validation took the CPG parameters with the smallest frequency
   error and only then checked the DSI PLL. A divider that lost on CPG
   error alone was never tried against the DSI PLL, so modes were
   rejected although another divider or PLL setting would have worked.
 - The PLLDSI divider's .determine_rate() runs its own search when the
   clock is set, so it can pick parameters other than the ones the DSI
   driver validated.

The first two patches add the clock-side support, the last two make the
DSI driver use it:

 1. Let the DSI driver cache the CPG divider parameters it validated,
    per PLLDSI instance, and have .determine_rate() reuse them when the
    requested rate matches.
 2. Add rzv2h_cpg_get_pll_pars_validate(), which offers each candidate
    to a callback and returns the first one it accepts.
    rzv2h_get_pll_pars() becomes a wrapper passing a NULL validator, so
    existing callers are unchanged.
 3. Evaluate every divider against the DSI PLL limits, keep the one with
    the smallest DSI PLL error and hand it to the CPG using the cache
    from patch 1.
 4. If no divider gives a usable pair, search again using patch 2 and
    take the first CPG candidate that is at most 50 Hz off at the PLLDSI
    output and gives a DSI HS clock error below 0.5 Hz. 50 Hz is at most
    2 ppm of the 25 MHz minimum PLLDSI output, so the pixel clock error
    stays negligible.

The cache in patch 1 is indexed by PLLDSI instance and shared by all CPG
instances, as the DSI driver only knows which instance it targets. If
there is a cleaner way to hand the parameters over to the CPG, I am
happy to rework it.

Testing
-------
"modetest -c" on [RZ/V2H EVK] (DSI -> ADV7535 -> HDMI, 4 lanes,
[monitor]) lists 27 modes instead of 21. No mode is lost, and these are
the newly usable ones:

  mode        refresh   pixel clock
  1920x1080   59.94 Hz  148352 kHz
  1280x720    59.94 Hz   74176 kHz
  720x480     60.00 Hz   27027 kHz
  640x480     60.00 Hz   25200 kHz
  640x480     59.94 Hz   25175 kHz
  720x400     70.08 Hz   28320 kHz

Dependencies
------------
Based on next-20261102 plus two patches from Tommaso that are not in
that tree:

  [1] clk: renesas: rzv2h: Forward PLLDSI mux rate requests to the parent
  [2] clk: renesas: rzv2h: Report the DSI duty cycle from the LVDS divider

[1] https://lore.kernel.org/all/20261029-tm-ssgrlpcsrc-2083-v5-clk-duty-fixes-v1-1-47f23de6bdb1@xxxxxxxxxxxxxx/
[2] https://lore.kernel.org/all/20261029-tm-ssgrlpcsrc-2083-v5-clk-duty-fixes-v1-2-47f23de6bdb1@xxxxxxxxxxxxxx/

Geert, Biju: I would suggest taking everything via renesas-clk
with an Ack from the DRM side, or providing an immutable branch with
patches 1-2 for the DRM tree. Please let me know which you prefer.

Cheers,
Prabhakar

Lad Prabhakar (4):
  clk: renesas: rzv2h-cpg: Allow MIPI DSI to reuse PLL divider
    parameters
  clk: renesas: rzv2h-cpg: Add validation hook to PLL parameter search
  drm: renesas: rz-du: mipi_dsi: Improve DSI PLL parameter selection and
    cache results
  drm: renesas: rz-du: mipi_dsi: Add fallback CPG PLLDSI parameter
    search

 drivers/clk/renesas/rzv2h-cpg-lib.c           | 109 ++++++++++-
 drivers/clk/renesas/rzv2h-cpg.c               |  15 +-
 .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c    | 174 +++++++++++++++---
 include/linux/clk/renesas.h                   |  38 ++++
 4 files changed, 300 insertions(+), 36 deletions(-)

-- 
2.56.0