[RFC PATCH v2 00/11] x86/resctrl: Support asymmetric L2 CAT on hybrid CPUs

[Tony Luck]

Stil RFC as it builds on Reinette's multiple control patches[0].

Some hybrid CPUs (e.g. Panther Lake) have L2 caches whose cache
allocation capabilities differ between P-core and E-core domains.
Today these show up as symmetric L2 CAT, on just the P-core. New CPUID
leaves enumerate asymmetric allocation separately, including per-domain
capacity bitmask (CBM) lengths.

This series teaches resctrl to use that enumeration:

 - Define the four Intel RDT CPUID leaves, and add the asymmetric
   L2 CAT/CDP feature bits, CPUID dependencies and rdt= boot options
   (l2cat_asym, l2cdp_asym).
 - Disable symmetric L2 CAT on Panther Lake, where it is misreported.
 - Clean up rdt_get_cache_alloc_cfg() (failure handling, leaf argument)
   and the RDT allocation feature checks to prepare for a second leaf.
 - Move the CBM length from the shared control to each control domain
   (touches fs/resctrl, x86 and MPAM) since lengths can now differ.
 - Enumerate asymmetric L2 CAT/CDP from CPUID leaf 0x28 when no
   shareable bits are reported (resctrl cannot represent them per
   domain). info/L2/cbm_mask reports the minimum CBM across domains.
 - Change the "max" file to show per-domain values, matching the
   schemata format, so the UI needs no change for asymmetric controls.
 - Document the new options and the cbm_mask semantics.

Changes since first RFC[1]:

*) No new/renamed resource or control. Just keep this as "L2" for both.

*) Keep the info/L2/cbm_mask but make it display the minimum mask across
   all domains. Naive legacy s/w may use this and waste some cache.

*) Chen Yu pointed out that I don't need to search the resource for the
   control to update the domain. Drop the helper and just update the
   bitmask length in domain_add_cpu_ctrl()

*) Find per-domain cbm_len for L3 as well as L2 cache (though still only
   look for asymmetric L2

*) Intel L2 caches don't have any shareable bits. Check that the
   shareable mask is zero (as this series doesn't update file system
   code to handle asymmetric shareable bits).

[0] Link: git://git.kernel.org/pub/scm/linux/kernel/git/reinette/linux.git resctrl/controls_rfc_v2.4
[1] Link: https://lore.kernel.org/all/auDiLEujZ5BGCACj@agluck-desk3/

Tony Luck (11):
  fs/resctrl: Change UI of "max" file (merge back into earlier patches)
  x86/resctrl: Disable symmetric L2 CAT on Panther Lake
  x86/cpuid: Define Intel RDT enumeration leaves
  x86/resctrl: Add asymmetric L2 CAT feature bits and boot options
  x86/resctrl: Handle cache allocation setup failures
  x86/resctrl: Pass the CPUID leaf to rdt_get_cache_alloc_cfg()
  arm,x86,fs/resctrl: Store cache bitmask length per control domain
  x86/resctrl: Use cpu_feature_enabled() for RDT allocation
  x86/resctrl: Accept asymmetric RDT allocation features
  x86/resctrl: Enable asymmetric CAT from CPUID leaf 0x28
  fs/resctrl: Document asymmetric L2 allocation options

 .../admin-guide/kernel-parameters.txt         |   3 +-
 Documentation/filesystems/resctrl.rst         |   8 +-
 include/linux/resctrl.h                       |  12 +-
 arch/x86/include/asm/cpufeatures.h            |   3 +
 arch/x86/include/asm/cpuid/types.h            |   4 +
 arch/x86/kernel/cpu/cpuid-deps.c              |   2 +
 arch/x86/kernel/cpu/resctrl/core.c            | 138 +++++++++++++-----
 arch/x86/kernel/cpu/resctrl/rdtgroup.c        |   2 +-
 arch/x86/kernel/cpu/scattered.c               |   3 +
 drivers/resctrl/mpam_resctrl.c                |  14 +-
 fs/resctrl/ctrlmondata.c                      |   9 +-
 fs/resctrl/pseudo_lock.c                      |   2 +-
 fs/resctrl/rdtgroup.c                         |  56 ++++---
 13 files changed, 184 insertions(+), 72 deletions(-)

-- 
2.56.0