[PATCH] dt-bindings: opp: Allow 'clock-latency' with dynamically populated OPPs

[Rob Herring (Arm)]

Tegra210 builds its CPU OPP table at runtime from fuse-derived process
and speedo values and built-in CVB coefficients. Its CPU node therefore
has clock-latency without a static operating-points property. The OPP
core still reads that latency when initializing the table.

Fixes: 80728bfa8c79 ("dt-bindings: arm/cpus: Add missing properties")
Signed-off-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
---
 Documentation/devicetree/bindings/opp/opp-v1.yaml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/opp/opp-v1.yaml b/Documentation/devicetree/bindings/opp/opp-v1.yaml
index 61c080e50859..3dca8f7f146d 100644
--- a/Documentation/devicetree/bindings/opp/opp-v1.yaml
+++ b/Documentation/devicetree/bindings/opp/opp-v1.yaml
@@ -24,7 +24,8 @@ properties:
   clock-latency:
     $ref: /schemas/types.yaml#/definitions/uint32
     description:
-      The latency in nanoseconds for clock changes. Use OPP tables for new
+      The latency in nanoseconds for clock changes. This also applies when
+      operating points are populated dynamically. Use OPP tables for new
       designs instead.
 
   voltage-tolerance:
@@ -41,7 +42,6 @@ properties:
         - description: Voltage for OPP in uV
 
 dependencies:
-  clock-latency: [ operating-points ]
   voltage-tolerance: [ operating-points ]
 
 additionalProperties: true
-- 
2.53.0