Re: [PATCH 2/2] phy: qcom: edp: update v8 power-on programming sequence

[Burke Cates]

On Sat, Oct 31, 2026 at 11:24:31AM -0500, Christian Cortner wrote:
> Writing the firmware values at the end of power-on, all 120 enables
> over two boots trained 4 lanes cleanly, and 10 of 10 resumes. Which
> register matters is not known. Happy to test a revision.

Same result on another Zenbook A16 (eDP at HBR2 x4): v7.4-rc1 with
Bjorn's v1 as posted (ldo_config 0xd0, not 0x91), out-of-tree Glymur
board patches, and your five values written after DCC. Link enables
with at least one failed training attempt, over fbdev blank/unblank
cycles and boots:

  without the values: 30 of 400 enables, 8 of 61 boots
  with the values:     0 of 500 enables, 0 of 162 boots

One dpu_encoder_virt_atomic_disable() "enc42 timeout pending" at a
blank (1 in 500) appeared only with the values; cause unknown.

AI coding assistants helped run these tests and draft this reply; the
results are from the hardware runs.

Thanks,
Burke