Re: [PATCH v5 1/3] dt-bindings: usb: Add CIX Sky1 USBSSP controller

From: Krzysztof Kozlowski

Date: Wed Nov 04 2026 - 02:51:25 EST


On 03/11/2026 08:49, Hongliang Yang (杨宏亮) wrote:
> Add device tree binding for the CIX Sky1 Cadence USBSSP controller
> glue layer. Each controller has an AXI bus attribute configuration
> register and a controller status register. The glue registers of the
> two controllers are interleaved inside a shared RCSU region, which is
> represented as a simple-bus container node with an address-translating

Shared region is not a simple bus. Simple bus is a simple bus, so
obviously is not a shared region.

> ranges property; each glue node describes its registers as offsets
> inside that region. Mode strap controls are programmed through the
> Sky1 S5 system controller referenced by the cix,usb-syscon phandle.
> The CIX glue node wraps a Cadence USBSSP core as a child node.
>


> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + usb-rcsu@91c0300 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x00 0x00000000 0x00 0x091c0300 0x00 0x150>,
> + <0x00 0x091d0000 0x00 0x091d0000 0x00 0x20000>;

Drop node. Not relevant.


> +
> + usb@14 {

So this is @14

> + compatible = "cix,sky1-usbssp";
> + reg = <0x00 0x14 0x00 0x10>,
> + <0x00 0x100 0x00 0x10>;
> + reg-names = "axi", "status";
> + ranges;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clocks = <&scmi_clk CLK_TREE_USB3A_H0_CLK_SOF>,
> + <&scmi_clk CLK_TREE_USB3A_0_AXI_GATE>,
> + <&scmi_clk CLK_TREE_USB3A_H0_CLK_LPM>,
> + <&scmi_clk CLK_TREE_USB3A_0_APB_GATE>;
> + clock-names = "sof", "axi", "lpm", "apb";
> + resets = <&src SKY1_USBC_SS2_PRST_N>,
> + <&src SKY1_USBC_SS2_RST_N>;
> + reset-names = "apb", "core";
> + cix,usb-syscon = <&src>;
> +
> + usb@91d0000 {

But this is at @91d0000

You have completely fake representation of hardware.


Best regards,
Krzysztof