Re: [PATCH 4/4] dmaengine: ti: cppi41: Share register setup with resume

[Adivi, Sai Sree Kartheek]

On 04/11/26 01:07, Markus Schneider-Pargmann (TI) wrote:
> Both probe and resume basically do the same thing and setup the
> registers. But resume has its own copy of the register writes. This will
> always lead to differences when changes are made.
>
> Create a separate function that is used by both probe and resume.
> Note that the ordering is slightly different but I didn't see or found
> any issues with the new order while testing.
>
> Signed-off-by: Markus Schneider-Pargmann (TI) <msp@xxxxxxxxxxxx>

Reviewed-by: Sai Sree Kartheek Adivi <s-adivi@xxxxxx>


> ---
>   drivers/dma/ti/cppi41.c | 41 ++++++++++++++++++++---------------------
>   1 file changed, 20 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/dma/ti/cppi41.c b/drivers/dma/ti/cppi41.c
> index e2a089066c6d..b62a26c2659d 100644
> --- a/drivers/dma/ti/cppi41.c
> +++ b/drivers/dma/ti/cppi41.c
> @@ -873,9 +873,6 @@ static int init_descs(struct device *dev, struct cppi41_dd *cdd)
>   				&cdd->descs_phys, GFP_KERNEL);
>   		if (!cdd->cd)
>   			return -ENOMEM;
> -
> -		cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
> -		cppi_writel(cppi41_memctrl(i), cdd->qmgr_mem + QMGR_MEMCTRL(i));
>   	}
>   	return 0;
>   }
> @@ -903,6 +900,24 @@ static void init_sched(struct cppi41_dd *cdd)
>   	cppi_writel(reg, cdd->sched_mem + DMA_SCHED_CTRL);
>   }
>   
> +/* Program the registers, also used to restore the context on resume */
> +static void cppi41_init_hw(struct cppi41_dd *cdd)
> +{
> +	int i;
> +
> +	cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
> +	cppi_writel(TOTAL_DESCS_NUM, cdd->qmgr_mem + QMGR_LRAM_SIZE);
> +	cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
> +
> +	for (i = 0; i < DESCS_AREAS; i++) {
> +		cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
> +		cppi_writel(cppi41_memctrl(i), cdd->qmgr_mem + QMGR_MEMCTRL(i));
> +	}
> +
> +	cppi_writel(cdd->td_queue.submit, cdd->ctrl_mem + DMA_TDFDQ);
> +	init_sched(cdd);
> +}
> +
>   static int init_cppi41(struct device *dev, struct cppi41_dd *cdd)
>   {
>   	int ret;
> @@ -913,16 +928,11 @@ static int init_cppi41(struct device *dev, struct cppi41_dd *cdd)
>   	if (!cdd->qmgr_scratch)
>   		return -ENOMEM;
>   
> -	cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
> -	cppi_writel(TOTAL_DESCS_NUM, cdd->qmgr_mem + QMGR_LRAM_SIZE);
> -	cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
> -
>   	ret = init_descs(dev, cdd);
>   	if (ret)
>   		goto err_td;
>   
> -	cppi_writel(cdd->td_queue.submit, cdd->ctrl_mem + DMA_TDFDQ);
> -	init_sched(cdd);
> +	cppi41_init_hw(cdd);
>   
>   	return 0;
>   err_td:
> @@ -1187,26 +1197,15 @@ static int __maybe_unused cppi41_resume(struct device *dev)
>   {
>   	struct cppi41_dd *cdd = dev_get_drvdata(dev);
>   	struct cppi41_channel *c;
> -	int i;
>   
>   	if (pm_runtime_status_suspended(dev))
>   		return 0;
>   
> -	for (i = 0; i < DESCS_AREAS; i++) {
> -		cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
> -		cppi_writel(cppi41_memctrl(i), cdd->qmgr_mem + QMGR_MEMCTRL(i));
> -	}
> -
>   	list_for_each_entry(c, &cdd->ddev.channels, chan.device_node)
>   		if (!c->is_tx)
>   			cppi_writel(c->q_num, c->gcr_reg + RXHPCRA0);
>   
> -	init_sched(cdd);
> -
> -	cppi_writel(cdd->td_queue.submit, cdd->ctrl_mem + DMA_TDFDQ);
> -	cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
> -	cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE);
> -	cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
> +	cppi41_init_hw(cdd);
>   
>   	cdd->ctx_lost = false;
>   
>