Re: [PATCH v7 10/12] serial: 8250_dw: discover Allwinner A523 FIFO depths through FCC

[Andy Shevchenko]

On Tue, Nov 03, 2026 at 02:40:03PM -0700, James Hilliard wrote:
> The A523 UART integration, also used by A527 and T527, has 64-byte FIFOs
> on UART0 and 128-byte FIFOs on UART1 through UART7. Each controller reports
> its TX/RX FIFO depth in bits 31:8 of the FIFO Clock Control register at
> offset 0xf0. The field holds a byte count, not a logarithmic encoding.
> 
> Read this field in the sunxi setup callback when platform data does not
> provide a fixed FIFO size. A fixed size takes precedence, so H616 retains
> its 256-byte configuration without accessing FCC. The probe has already
> enabled the clocks and deasserted reset before invoking the callback.
> Leave the FIFO clock-control bits untouched.
> 
> Use the shared DesignWare trigger setup to validate the depth and build
> the FIFO-relative threshold table. Invalid depths fail probe before
> registration instead of producing zero or truncated thresholds. The 8250
> core derives the transmit load from the discovered depth.
> 
> Select this setup for the A523 compatible. Like H616, this integration
> has Allwinner-specific debug-divisor and RS485 registers overlapping the
> generic DesignWare feature probes. Use the common sunxi PIO setup,
> BUSY-safe integer divisor programming and software RS485 handling. Keep
> the APB clock gate enabled during termios updates with SKIP_SET_RATE.

...

>  	p->type = PORT_16550A;
>  	p->flags |= UPF_FIXED_TYPE;

+ Blank line in this patch.

> -	p->fifosize = data->pdata->fifo_size;

Perhaps a comment here

	/* Apply given FIFO size or try to autodetect it */

> +	if (data->pdata->fifo_size) {
> +		p->fifosize = data->pdata->fifo_size;
> +	} else {
> +		u32 fcc = dw8250_readl_ext(p, SUNXI_UART_FCC);
> +
> +		p->fifosize = FIELD_GET(SUNXI_UART_FCC_FIFO_DEPTH, fcc);
> +	}

Add a blank line here in the previous patch.

>  	up->capabilities = UART_CAP_FIFO | UART_CAP_NOTEMT | UART_CAP_AFE;

...

Otherwise LGTM.

-- 
With Best Regards,
Andy Shevchenko