Re: [PATCH v2 1/5] dt-bindings: phy: qcom: Add common qcom,csi2-phy

[Bryan O'Donoghue]

On 03/11/2026 21:41, Anusha Arun Nandi wrote:
> SA8775P, QCS8300 and SC7280 CSI2 PHYs are bit-for-bit identical in
> devicetree shape (ports, bus-type, data-lanes, operating-points-v2,
> clocks, single "top" power-domain, vdda-phy/vdda-pll supplies).
>
> Describe all three with a single qcom,csi2-phy.yaml and a compatible
> oneOf, rather than one standalone schema per SoC. QCS8300 is further
> required to be paired with a qcom,sa8775p-csi2-phy fallback
> compatible, the same way other Qualcomm bindings express full
> hardware compatibility between two SoCs (see qcom,qusb2-phy.yaml);
> this lets the driver bind QCS8300 nodes via its qcom,sa8775p-csi2-phy
> match entry rather than carrying a duplicate one.
>
> qcom,x1e80100-csi2-phy.yaml is a separate PHY with a different shape
> (3 clocks, 3 power-domains, different supply names, DPHY split-mode
> support) and is left untouched.
>
> Reviewed-by: Jigarkumar Zala <jigarkumar.zala@xxxxxxxxxxxxxxxx>
> Signed-off-by: Anusha Arun Nandi <anusha.nandi@xxxxxxxxxxxxxxxx>
> ---
>   .../bindings/phy/qcom,csi2-phy.yaml           | 176 ++++++++++++++++++
>   1 file changed, 176 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/phy/qcom,csi2-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,csi2-phy.yaml
> new file mode 100644
> index 000000000000..5d25547528bd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,csi2-phy.yaml
> @@ -0,0 +1,176 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,csi2-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm CSI2 PHY
> +
> +maintainers:
> +  - Anusha Arun Nandi <anusha.nandi@xxxxxxxxxxxxxxxx>
> +
> +description:
> +  Qualcomm MIPI CSI2 D-PHY. Connects MIPI CSI2 sensors to Qualcomm's Camera
> +  CSI Decoder.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - enum:
> +          - qcom,sa8775p-csi2-phy
> +          - qcom,sc7280-csi2-phy
> +      - items:
> +          - enum:
> +              - qcom,qcs8300-csi2-phy
> +          - const: qcom,sa8775p-csi2-phy
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 2
> +
> +  clock-names:
> +    items:
> +      - const: core
> +      - const: timer
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  operating-points-v2: true
> +
> +  opp-table:
> +    type: object
> +
> +  power-domains:
> +    items:
> +      - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
> +
> +  power-domain-names:
> +    items:
> +      - const: top
> +
> +  vdda-phy-supply:
> +    description: Phandle to PHY supply.
> +
> +  vdda-pll-supply:
> +    description: Phandle to PLL supply.

Why are we departing from vdda-0p9-supply and vdda-1p2-supply ?

Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml

> +
> +  ports:
> +    $ref: /schemas/graph.yaml#/properties/ports
> +
> +    properties:
> +      port@0:
> +        $ref: /schemas/graph.yaml#/$defs/port-base
> +        description:
> +          Sensor input. A single sensor is described by a single endpoint
> +          with one to four data lanes, numbered 1-4. The clock lane is
> +          position 0.

Since you've cloned and owned the yaml - you've also dropped the 
description of DPHY split mode.

> +
> +        unevaluatedProperties: false
> +
> +        properties:
> +          endpoint:
> +            $ref: /schemas/media/video-interfaces.yaml#
> +            unevaluatedProperties: false
> +            properties:
> +              bus-type:
> +                enum:
> +                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
> +                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
> +                default: 4
> +
> +              data-lanes:
> +                minItems: 1
> +                maxItems: 4
> +                items:
> +                  minimum: 1
> +                  maximum: 4
> +                description:
> +                  Data lane positions following this endpoint's clock
> +                  lane. Positions are a per-port logical numbering, not
> +                  package pad or ball positions.
> +
> +            required:
> +              - data-lanes
> +              - remote-endpoint

And then you've dropped the DPHY split mode defintion

NAK

Please either clone and own the whole DPHY split-mode circus or just 
modify the existing definition to include your new stuff.

> +
> +      port@1:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description: Output to the CAMSS CSID controller.
> +
> +    required:
> +      - port@0
> +      - port@1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - interrupts
> +  - operating-points-v2
> +  - power-domains
> +  - power-domain-names
> +  - vdda-phy-supply
> +  - vdda-pll-supply
> +  - ports
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/media/video-interfaces.h>
> +
> +    phy@ac9c000 {
> +        compatible = "qcom,sa8775p-csi2-phy";
> +        reg = <0x0ac9c000 0x2000>;
> +
> +        clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
> +                 <&camcc CAM_CC_CSI0PHYTIMER_CLK>;
> +        clock-names = "core",
> +                      "timer";
> +
> +        interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
> +
> +        operating-points-v2 = <&csiphy_opp_table>;
> +
> +        power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +        power-domain-names = "top";
> +
> +        vdda-phy-supply = <&vreg_l4a>;
> +        vdda-pll-supply = <&vreg_l1c>;
> +
> +        ports {
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            port@0 {
> +                reg = <0>;
> +                csiphy0_in: endpoint {
> +                    bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
> +                    data-lanes = <1 2 3 4>;
> +                    remote-endpoint = <&sensor_out>;
> +                };
> +            };
> +
> +            port@1 {
> +                reg = <1>;
> +                csiphy0_out: endpoint {
> +                    remote-endpoint = <&csid_in>;
> +                };
> +            };
> +        };
> +
> +        csiphy_opp_table: opp-table {
> +            compatible = "operating-points-v2";
> +
> +            opp-300000000 {
> +                opp-hz = /bits/ 64 <300000000>;
> +            };
> +        };
> +    };
> --
> 2.34.1