Re: [PATCH 2/2] clk: renesas: r9a09g056: Add ADC clocks and reset
From: Geert Uytterhoeven
Date: Wed Nov 04 2026 - 11:47:47 EST
Hi Prabhakar,
On Tue, 29 Sept 2026 at 13:39, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Add clocks and reset entries for the ADC controller.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Thanks for your patch!
Similar comments as for "[PATCH 1/2] clk: renesas: r9a09g057: Add ADC
clocks and reset".
> --- a/drivers/clk/renesas/r9a09g056-cpg.c
> +++ b/drivers/clk/renesas/r9a09g056-cpg.c
> @@ -539,6 +556,10 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
> BUS_MSTOP(3, BIT(4))),
> DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
> BUS_MSTOP(3, BIT(4))),
> + DEF_MOD("adc_0_pclk", CLK_PLLCM33_ADC_PCLK_DIV2, 16, 7, 8, 7,
> + BUS_MSTOP(3, BIT(9))),
> + DEF_MOD("adc_0_adclk", CLK_PLLCM33_ADC_ADCLK_GEAR, 16, 8, 8, 8,
> + BUS_MSTOP(3, BIT(9))),
> DEF_MOD("tsu_0_pclk", CLK_QEXTAL, 16, 9, 8, 9,
> BUS_MSTOP(5, BIT(2))),
> DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10,
> @@ -634,6 +655,7 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
> DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */
> DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */
> DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */
> + DEF_RST(15, 6, 7, 7), /* ADC_ADRST_N */
> DEF_RST(15, 7, 7, 8), /* TSU_0_PRESETN */
> DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */
> };
The lists of clock and reset signals (tables 4.4-2 and 4.4-3) claim
there are 3 sets of clocks and resets, one for each ADC instance,
but this does not seem to be reflected in the register bits?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds