[PATCH v13 5/8] thermal/qcom/lmh: Add support for Qualcomm SM7250

[Sreeshankar K]

Qualcomm SM7250 features an asymmetric 6+2 core topology where the
Silver cluster consists of CPU 0 to CPU 5 and the Gold/Prime cluster
starts at logical CPU 6.

Add the SoC match data defining the CPU-to-node mapping (CPU 0 to
LMH_CLUSTER0_NODE_ID, and CPU 6 to LMH_CLUSTER1_NODE_ID), and register
the "qcom,sm7250-lmh" compatible string so both LMh cluster instances
can probe and register their respective DCVSh interrupt domains.

Signed-off-by: Sreeshankar K <sreeshankar0910@xxxxxxxxx>
---
 drivers/thermal/qcom/lmh.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/thermal/qcom/lmh.c b/drivers/thermal/qcom/lmh.c
index ef49ed1c6..ad6d34b8e 100644
--- a/drivers/thermal/qcom/lmh.c
+++ b/drivers/thermal/qcom/lmh.c
@@ -110,12 +110,22 @@ static const struct qcom_lmh_node_map sdm845_lmh_map[] = {
 	{ .cpu_id = 4, .node_id = LMH_CLUSTER1_NODE_ID },
 };
 
+static const struct qcom_lmh_node_map sm7250_lmh_map[] = {
+	{ .cpu_id = 0, .node_id = LMH_CLUSTER0_NODE_ID },
+	{ .cpu_id = 6, .node_id = LMH_CLUSTER1_NODE_ID },
+};
+
 static const struct qcom_lmh_soc_data sdm845_lmh_data = {
 	.map = sdm845_lmh_map,
 	.num_nodes = ARRAY_SIZE(sdm845_lmh_map),
 	.flags = LMH_ENABLE_ALGOS,
 };
 
+static const struct qcom_lmh_soc_data sm7250_lmh_data = {
+	.map = sm7250_lmh_map,
+	.num_nodes = ARRAY_SIZE(sm7250_lmh_map),
+};
+
 static const struct qcom_lmh_soc_data sm8150_lmh_data = {
 	.map = sdm845_lmh_map,
 	.num_nodes = ARRAY_SIZE(sdm845_lmh_map),
@@ -124,6 +134,7 @@ static const struct qcom_lmh_soc_data sm8150_lmh_data = {
 static const struct of_device_id lmh_table[] = {
 	{ .compatible = "qcom,sc8180x-lmh", .data = &sm8150_lmh_data },
 	{ .compatible = "qcom,sdm845-lmh", .data = &sdm845_lmh_data },
+	{ .compatible = "qcom,sm7250-lmh",  .data = &sm7250_lmh_data },
 	{ .compatible = "qcom,sm8150-lmh",  .data = &sm8150_lmh_data },
 	{}
 };

-- 
2.43.0