Re: [PATCH v7 5/7] dmaengine: dw-edma: Use HDMA watermark interrupts as LL progress

[Frank Li]

On Thu, Nov 05, 2026 at 01:12:25AM +0900, Koichiro Den wrote:
> While HDMA is running, DMA_LLP is updated only at watermark events.
> Enable watermark interrupts to track progress without waiting for the
> channel to stop.
>
> Set the watermark bits on entries that request an interrupt, configure
> local or remote delivery, and pass events to the LL progress handler.
> Unmask local watermark interrupts only for LL channels in local IRQ mode.
>
> Signed-off-by: Koichiro Den <den@xxxxxxxxxxxxx>
> ---

Reviewed-by: Frank Li <Frank.Li@xxxxxxx>

> Changes from v6:
>   - Keep watermark interrupts masked for non-LL channels (Sashiko).
>   - Link to v6: https://lore.kernel.org/r/20261030150742.2586776-4-den@xxxxxxxxxxxxx/
>
> Note: Since v6, IRQ placement has been limited to descriptor ends and
>       the last free entry to keep the series small. Further tuning can
>       be done in follow-up patches. I should've mentioned this in v6
>       when dropping v5 patch 14:
>       https://lore.kernel.org/r/20260812155721.2807506-15-den@xxxxxxxxxxxxx/
>
>  drivers/dma/dw-edma/dw-hdma-v0-core.c | 62 ++++++++++++++++++++++-----
>  drivers/dma/dw-edma/dw-hdma-v0-regs.h |  1 +
>  2 files changed, 52 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c
> index aa430219d0af..0cccd0003a1b 100644
> --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c
> +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c
> @@ -58,7 +58,8 @@ static u32 dw_hdma_v0_core_int_setup(struct dw_edma_chan *chan, u32 val)
>  {
>  	val &= ~(HDMA_V0_LOCAL_ABORT_INT_EN | HDMA_V0_REMOTE_ABORT_INT_EN |
>  		 HDMA_V0_LOCAL_STOP_INT_EN | HDMA_V0_REMOTE_STOP_INT_EN |
> -		 HDMA_V0_ABORT_INT_MASK | HDMA_V0_STOP_INT_MASK);
> +		 HDMA_V0_ABORT_INT_MASK | HDMA_V0_WATERMARK_INT_MASK |
> +		 HDMA_V0_STOP_INT_MASK);
>
>  	/*
>  	 * HDMA_INT_STATUS.STOP and .ABORT are latched only when LSIE and
> @@ -68,6 +69,9 @@ static u32 dw_hdma_v0_core_int_setup(struct dw_edma_chan *chan, u32 val)
>  	 */
>  	val |= HDMA_V0_LOCAL_ABORT_INT_EN | HDMA_V0_LOCAL_STOP_INT_EN;
>
> +	if (chan->non_ll || chan->irq_mode == DW_EDMA_CH_IRQ_REMOTE)
> +		val |= HDMA_V0_WATERMARK_INT_MASK;
> +
>  	if (chan->irq_mode == DW_EDMA_CH_IRQ_REMOTE)
>  		val |= HDMA_V0_REMOTE_ABORT_INT_EN |
>  		       HDMA_V0_REMOTE_STOP_INT_EN |
> @@ -81,10 +85,12 @@ static void dw_hdma_v0_core_ch_off(struct dw_edma *dw, enum dw_edma_dir dir,
>  				   u16 id)
>  {
>  	SET_CH_32(dw, dir, id, int_setup,
> -		  HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK);
> +		  HDMA_V0_STOP_INT_MASK | HDMA_V0_WATERMARK_INT_MASK |
> +		  HDMA_V0_ABORT_INT_MASK);
>  	SET_CH_32(dw, dir, id, ch_en, 0);
>  	SET_CH_32(dw, dir, id, int_clear,
> -		  HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK);
> +		  HDMA_V0_STOP_INT_MASK | HDMA_V0_WATERMARK_INT_MASK |
> +		  HDMA_V0_ABORT_INT_MASK);
>  }
>
>  static void dw_hdma_v0_core_off(struct dw_edma *dw)
> @@ -95,18 +101,26 @@ static void dw_hdma_v0_core_off(struct dw_edma *dw)
>  	dir = EDMA_DIR_WRITE;
>  	for (id = 0; id < dw->wr_ch_cnt; id++) {
>  		SET_CH_32(dw, dir, id, int_setup,
> -			  HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK);
> +			  HDMA_V0_STOP_INT_MASK |
> +			  HDMA_V0_WATERMARK_INT_MASK |
> +			  HDMA_V0_ABORT_INT_MASK);
>  		SET_CH_32(dw, dir, id, int_clear,
> -			  HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK);
> +			  HDMA_V0_STOP_INT_MASK |
> +			  HDMA_V0_WATERMARK_INT_MASK |
> +			  HDMA_V0_ABORT_INT_MASK);
>  		SET_CH_32(dw, dir, id, ch_en, 0);
>  	}
>
>  	dir = EDMA_DIR_READ;
>  	for (id = 0; id < dw->rd_ch_cnt; id++) {
>  		SET_CH_32(dw, dir, id, int_setup,
> -			  HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK);
> +			  HDMA_V0_STOP_INT_MASK |
> +			  HDMA_V0_WATERMARK_INT_MASK |
> +			  HDMA_V0_ABORT_INT_MASK);
>  		SET_CH_32(dw, dir, id, int_clear,
> -			  HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK);
> +			  HDMA_V0_STOP_INT_MASK |
> +			  HDMA_V0_WATERMARK_INT_MASK |
> +			  HDMA_V0_ABORT_INT_MASK);
>  		SET_CH_32(dw, dir, id, ch_en, 0);
>  	}
>  }
> @@ -168,6 +182,14 @@ static void dw_hdma_v0_core_clear_done_int(struct dw_edma_chan *chan)
>  	SET_CH_32(dw, chan->dir, chan->id, int_clear, HDMA_V0_STOP_INT_MASK);
>  }
>
> +static void dw_hdma_v0_core_clear_watermark_int(struct dw_edma_chan *chan)
> +{
> +	struct dw_edma *dw = chan->dw;
> +
> +	SET_CH_32(dw, chan->dir, chan->id, int_clear,
> +		  HDMA_V0_WATERMARK_INT_MASK);
> +}
> +
>  static void dw_hdma_v0_core_clear_abort_int(struct dw_edma_chan *chan)
>  {
>  	struct dw_edma *dw = chan->dw;
> @@ -208,17 +230,23 @@ dw_hdma_v0_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir,
>  			continue;
>
>  		val = dw_hdma_v0_core_status_int(chan);
> -		if (FIELD_GET(HDMA_V0_STOP_INT_MASK, val)) {
> +
> +		if (FIELD_GET(HDMA_V0_STOP_INT_MASK, val))
>  			dw_hdma_v0_core_clear_done_int(chan);
> -			handler(chan, DW_EDMA_IRQ_STOP);
> +		if (FIELD_GET(HDMA_V0_WATERMARK_INT_MASK, val))
> +			dw_hdma_v0_core_clear_watermark_int(chan);
>
> +		if (FIELD_GET(HDMA_V0_STOP_INT_MASK, val)) {
> +			handler(chan, DW_EDMA_IRQ_STOP);
> +			ret = IRQ_HANDLED;
> +		} else if (FIELD_GET(HDMA_V0_WATERMARK_INT_MASK, val)) {
> +			handler(chan, DW_EDMA_IRQ_PROGRESS);
>  			ret = IRQ_HANDLED;
>  		}
>
>  		if (FIELD_GET(HDMA_V0_ABORT_INT_MASK, val)) {
>  			dw_hdma_v0_core_clear_abort_int(chan);
>  			handler(chan, DW_EDMA_IRQ_ABORT);
> -
>  			ret = IRQ_HANDLED;
>  		}
>  	}
> @@ -275,7 +303,7 @@ static void dw_hdma_v0_core_ch_enable(struct dw_edma_chan *chan)
>
>  	/* Enable engine */
>  	SET_CH_32(dw, chan->dir, chan->id, ch_en, BIT(0));
> -	/* Interrupt unmask - stop, abort */
> +	/* Interrupt unmask - stop, watermark, abort */
>  	tmp = GET_CH_32(dw, chan->dir, chan->id, int_setup);
>  	tmp = dw_hdma_v0_core_int_setup(chan, tmp);
>  	SET_CH_32(dw, chan->dir, chan->id, int_setup, tmp);
> @@ -336,6 +364,11 @@ static void dw_hdma_v0_core_ch_config(struct dw_edma_chan *chan)
>  	/* MSI done addr - low, high */
>  	SET_CH_32(dw, chan->dir, chan->id, msi_stop.lsb, chan->msi.address_lo);
>  	SET_CH_32(dw, chan->dir, chan->id, msi_stop.msb, chan->msi.address_hi);
> +	/* MSI watermark addr - low, high */
> +	SET_CH_32(dw, chan->dir, chan->id, msi_watermark.lsb,
> +		  chan->msi.address_lo);
> +	SET_CH_32(dw, chan->dir, chan->id, msi_watermark.msb,
> +		  chan->msi.address_hi);
>  	/* MSI abort addr - low, high */
>  	SET_CH_32(dw, chan->dir, chan->id, msi_abort.lsb, chan->msi.address_lo);
>  	SET_CH_32(dw, chan->dir, chan->id, msi_abort.msb, chan->msi.address_hi);
> @@ -355,6 +388,13 @@ dw_hdma_v0_core_ll_data(struct dw_edma_chan *chan, struct dw_edma_burst *burst,
>  	if (cb)
>  		control |= DW_HDMA_V0_CB;
>
> +	if (irq) {
> +		control |= DW_HDMA_V0_LWIE;
> +
> +		if (chan->irq_mode == DW_EDMA_CH_IRQ_REMOTE)
> +			control |= DW_HDMA_V0_RWIE;
> +	}
> +
>  	dw_hdma_v0_write_ll_data(chan, idx, control, burst->sz, burst->sar,
>  				 burst->dar);
>  }
> diff --git a/drivers/dma/dw-edma/dw-hdma-v0-regs.h b/drivers/dma/dw-edma/dw-hdma-v0-regs.h
> index b88226cdd791..e240ffb3dea7 100644
> --- a/drivers/dma/dw-edma/dw-hdma-v0-regs.h
> +++ b/drivers/dma/dw-edma/dw-hdma-v0-regs.h
> @@ -18,6 +18,7 @@
>  #define HDMA_V0_LOCAL_STOP_INT_EN		BIT(4)
>  #define HDMA_V0_REMOTE_STOP_INT_EN		BIT(3)
>  #define HDMA_V0_ABORT_INT_MASK			BIT(2)
> +#define HDMA_V0_WATERMARK_INT_MASK		BIT(1)
>  #define HDMA_V0_STOP_INT_MASK			BIT(0)
>  #define HDMA_V0_LINKLIST_EN			BIT(0)
>  #define HDMA_V0_CONSUMER_CYCLE_STAT		BIT(1)
> --
> 2.54.0
>