Re: [PATCH 1/2] clk: divider: Fix the divisor for rates above 4.29 GHz

[Brian Masney]

> DIV_ROUND_UP_ULL() takes a 32-bit divisor, so on 64-bit platforms a
> requested rate above 4.29 GHz is truncated. A divider fed by a 5.94 GHz
> PLL then computes a divisor of 7, not 1, for 5.94 GHz.
> 
> Use DIV64_U64_ROUND_UP(), which takes a 64-bit divisor.
> 
> Fixes: 9556f9dad8f5 ("clk: divider: handle integer overflow when dividing large clock rates")
> Signed-off-by: Sebastian Reichel <sebastian.reichel@xxxxxxxxxxxxx>
> Signed-off-by: Carlo Caione <ccaione@xxxxxxxxxxxx>

Reviewed-by: Brian Masney <masneyb@xxxxxxxxxx>

Since this is a core change to the framework, I'd also like to see what
Jerome thinks before we merge this.

Brian

-- 
Brian Masney <masneyb@xxxxxxxxxx>