Re: [PATCH 3/4] dt-bindings: clock: Add Siflower SF19A2890 peripheral clock/reset managers

[Conor Dooley]

On Wed, Nov 04, 2026 at 08:08:57PM -0500, Joseph Telaak wrote:
> > This binding looks like things that we often see that are actually
> > incorrect models of the devices in question - things that should be a
> > syscon but not implemented as one. I'd like to see what the actual dts
> > for this device looks like before signing off (or really even reviewing
> > this at all). Given how the clocks look, it is probably accurate but I
> > wanna be sure.
> 
> The dts is a separate series I'm holding until the bindings settle. In
> it, each manager is a node like this one:

Just link me a tree somewhere with the dts, I;m sure one exists ;)

> 
> uart_crm: clock-controller@19e24c00 {
> compatible = "siflower,sf19a2890-uart-crm";
> reg = <0x19e24c00 0x10>;
> clocks = <&clk CLK_MUXDIV_PBUS>, <&clk CLK_MUXDIV_PBUS>,
> <&clk CLK_MUXDIV_PBUS>, <&clk CLK_MUXDIV_UART>,
> <&clk CLK_MUXDIV_UART>, <&clk CLK_MUXDIV_UART>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> };
> 
> with twelve of them, at 0x19e04400 (gmac), 0x19e08000 (wlan24),
> 0x19e08800 (rf), 0x19e0c000 (usb), 0x19e0c400 (wlan5), 0x19e24400 (i2c),
> 0x19e24800 (spi), 0x19e24c00 (uart), 0x19e25400 (pwm), 0x19e25800
> (timer), 0x19e25c00 (wdt) and 0x19e2b400 (gpio).
> 
> You may well be right. I dumped the first 256 bytes of each block from
> U-Boot: all twelve have the same four registers at 0x0-0xc (reset, clock
> gate, one I have no documentation for, and bus output enable), and five
> have more past that: the GMAC's interface and RGMII delay registers at
> 0x40-0x4c, the USB PHY's at 0x40-0x8c, one register at 0x50 in each WLAN
> block, and two at 0x48 in the SPI block. So each block looks like a
> small system controller for its peripheral, with the clock and reset
> manager at its start.
> 
> If that should be one syscon node per block, providing the clocks and

No probably not.

> resets and holding the peripheral's control registers, I'll restructure
> the binding, the GMAC glue and the USB PHY that way. I can also post the
> dts series now if that helps.

Attachment: signature.asc
Description: PGP signature