RE: [PATCH RESEND v3] mtd: spi-nor: micron-st: Add support for is25wx01g

[Takahiro.Kuwano]

Hi,

> Add support for the ISSI IS25WX01G, a 1 Gbit (128 MiB) octal NOR flash.
> The part is fully described by SFDP, so only the flash ID and a small
> post_bfpt fixup are needed.
> 
> WRITE STATUS REGISTER (01h) takes a single data byte and only affects
> status register bits 7:2, so the default 16-bit Write Status assumption
> does not hold. Clear write_sr1_and_sr2 so that the single byte write_sr1
> path is taken; write_sr1 is already set to 01h by the BFPT parsing.
> 
> The flash also has no Status Register 2. Configuration registers are read
> with B5h/85h and written with B1h/81h, and the 35h Read Configuration
> Register command does not exist, so clear read_sr2 as well.
> 
> Software write protection is done through the block protect bits in the
> status register: BP0-BP2 at bits 4:2, BP3 at bit 6 and a Top/Bottom bit at
> bit 5, which is exactly what SPI_NOR_HAS_LOCK, SPI_NOR_4BIT_BP,
> SPI_NOR_BP3_SR_BIT6 and SPI_NOR_HAS_TB describe, so set those flags to get
> the generic locking support.
> 
> Note that given that the Flag Status Register (FSR) handling is the same
> as in some micron devices, were're adding the issi chip directly on the
> micron-st driver.
> 
> Signed-off-by: Nuno Sá <nuno.sa@xxxxxxxxxx>

Please add Link: tag as Michael mentioned in [1].

[...]

> @@ -655,6 +680,7 @@ static const struct spi_nor_fixups micron_st_nor_fixups = {
> 
>  static const struct spi_nor_fixup micron_fixups[] = {
>         { .fixups = &micron_st_nor_fixups },
> +       { .id = SNOR_ID(0x9d, 0x5b, 0x1b), .fixups = &is25wx01g_fixups },

Sashiko's comment [2] looks valid to me as this chip supports 8D-8D-8D.
Could you please take a look?

Thanks,
Takahiro

[1] https://lore.kernel.org/linux-mtd/DLETRRVRUWEP.1VU1EHARD3MSH@xxxxxxxxxx/
[2] https://sashiko.dev/#/patchset/20261102-mtd-spi-nor-new-issi-chip-v3-1-f5e38e200fc8%40analog.com