Re: [PATCH 1/2] gpio: aspeed: Clear only the acked line's G4 interrupt status

[Andrew Jeffery]

On Wed, 2026-11-04 at 11:58 +0800, Billy Tsai wrote:
> The G4 interrupt status registers are write-1-to-clear: writing 0 to a
> bit has no effect and writing 1 clears that line's status flag.
> aspeed_gpio_irq_ack() clears a line's status through
> aspeed_g4_reg_bit_set(), which reads the bank's status register, sets
> the line's bit and writes the whole value back. That write clears every
> interrupt pending in the 32-line bank, not just the acked one.
> 
> aspeed_gpio_irq_handler() reads each bank's status register once and
> dispatches the lines that were set. If another line in the same bank
> latches an edge after that read and before an ack in the bank, the ack
> clears its status and the handler is never called for it, so the edge
> is lost.
> 
> Write only the line's own bit when clearing the interrupt status on G4.
> 
> Fixes: 79fc9a2fcc45 ("gpio: aspeed: Create llops to handle hardware access")
> Cc: stable@xxxxxxxxxxxxxxx
> Reported-by: Aaron Antone <aae@xxxxxxxxxx>
> Suggested-by: Aaron Antone <aae@xxxxxxxxxx>

Reviewed-by: Andrew Jeffery <andrew@xxxxxxxxxxxxxxxxxxxx>
Tested-by: Andrew Jeffery <andrew@xxxxxxxxxxxxxxxxxxxx>