Re: [PATCH v6 0/3] phy: Add CIX Sky1 USB3 PHY support

[Krzysztof Kozlowski]

On Thu, Nov 05, 2026 at 01:17:56AM +0000, Hongliang Yang (杨宏亮) wrote:
> This series adds support for the USB3 PHY integrated in the CIX Sky1
> SoC.
> 
> Patch 1 adds the device tree binding, patch 2 the PHY driver, and
> patch 3 the SoC node plus the board enablement.
> 
> The PHY provides the SuperSpeed lanes for the Cadence USBSSP
> controllers of the SoC. The block drives both USB3 lanes: it is
> exposed as a single PHY provider with #phy-cells = <0>, and its
> init/exit calls are reference counted so that both controllers can
> share it.
> 
> Tested on Radxa Orion O6 (Sky1) together with the USBSSP controller
> series: the PHY probes and USB 3.x devices enumerate at SuperSpeed.
> 
> The controller device tree nodes use the PHY phandle added here; the
> USBSSP controller series is posted separately.
> 
> The series applies on top of v7.4-rc1.
> 
> Changes in v6:
> - Drop the per-port child nodes; the PHY provider node itself is
>   referenced with #phy-cells = <0> and the driver exports a single
>   PHY instance shared by both controllers.
> - Select REGMAP in the PHY Kconfig.
> - Use dev_err_probe() for the reset, clock and regmap acquisition
>   failures in the probe path.
> - Corrected the mail sender name: v5 was sent with a non-ASCII
>   display name in the From header, v6 uses the plain ASCII name
>   that matches the Signed-off-by.

No, you did not.

Best regards,
Krzysztof