Re: [PATCH v6 08/15] drm/rockchip: vop2: Consolidate HDMI PHY PLL clock parent switch

[Cristian Ciocaltea]

Hi,

On 11/5/26 2:18 PM, Daniel Stone wrote:
> Hi,
> 
> On Thu, 5 Nov 2026 at 01:01, Cristian Ciocaltea
> <cristian.ciocaltea@xxxxxxxxxxxxx> wrote:
>> +               if (pll_hdmiphy) {
>> +                       ret = clk_set_parent(vp->dclk, pll_hdmiphy);
>> +                       if (ret < 0)
>> +                               drm_warn(vop2->drm,
>> +                                        "Failed to switch DCLK to HDMI PHY PLL: %d\n",
>> +                                        ret);
>> +               }
> 
> I'm confused ... if we have switched to the PHY for dclk, then a mode
> switch wants us to come back to the CRU source, don't we need to
> reparent to dclk_src?

This is actually done in vop2_crtc_atomic_disable():

    if (vp->dclk_src)
        clk_set_parent(vp->dclk, vp->dclk_src);

Mostly to ensure the PHY related resources are released when not in use, e.g.
after unplugging the display.

Thanks,
Cristian