[PATCH 5/5] arm64: dts: qcom: ipq5210: Add NSS clock controller node

From: Luo Jie

Date: Thu Nov 05 2026 - 08:30:51 EST


NSS clock controller provides the clocks and resets to the networking
hardware blocks on the IPQ5210, such as PPE (Packet Process Engine) and
the integrated EPHY.

Note that the CMN PLL output clock names are reversed with respect to the
hardware block they actually feed: IPQ5210_PPE_CLK is wired to the NSS
hardware block, and IPQ5210_NSS_CLK is wired to the PPE hardware block.
Documentation is added in the DTS file to call this out and avoid
confusion.

Signed-off-by: Luo Jie <jie.luo@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/ipq5210.dtsi | 40 +++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
index 0c1ede0f73b2..11915f8eb156 100644
--- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
@@ -331,6 +331,46 @@ frame@b128000 {
status = "disabled";
};
};
+
+ nsscc: clock-controller@39b00000 {
+ compatible = "qcom,ipq5210-nsscc";
+ reg = <0x0 0x39b00000 0x0 0x100000>;
+ /*
+ * Note: CMN PLL output clock names below are reversed relative
+ * to the hardware block they feed - IPQ5210_PPE_CLK is wired to
+ * the NSS hardware block ("nss") and IPQ5210_NSS_CLK is wired
+ * to the PPE hardware block ("ppe").
+ */
+ clocks = <&xo_board>,
+ <&cmn_pll IPQ5210_PPE_CLK>,
+ <&cmn_pll IPQ5210_NSS_CLK>,
+ <&gcc GPLL0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <&gcc GCC_NSSCC_CLK>,
+ <&cmn_pll IPQ5210_EPHY_RAW_CLK>,
+ <&cmn_pll IPQ5210_EPHY_RAW_CLK>;
+ clock-names = "xo",
+ "nss",
+ "ppe",
+ "gpll0_out",
+ "uniphy0_rx",
+ "uniphy0_tx",
+ "uniphy1_rx",
+ "uniphy1_tx",
+ "uniphy2_rx",
+ "uniphy2_tx",
+ "bus",
+ "ephy_rx",
+ "ephy_tx";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #interconnect-cells = <1>;
+ };
};

timer {

--
2.43.0