[PATCH 5/5] arm64: dts: qcom: sm8350: Add the GPU speed bins
From: Demeter Barna via B4 Relay
Date: Thu Nov 05 2026 - 08:36:41 EST
From: Demeter Barna <me@xxxxxxxxxxxxxxxxxxx>
Today every SM8350 runs its GPU up to 840 MHz, including the parts that
are validated only up to 738 MHz, and no part gets the 900 MHz level the
best bin supports.
Describe the QFPROM with the GPU speed bin cell, as sm8250.dtsi does,
let the GPU read it and mark each OPP with the bins that support it:
900 MHz bin 1 (new OPP, same bandwidth as 840 MHz)
840, 778 MHz bins 0 and 1
738 MHz and below all bins
Drop the note about downstream binning above the OPP table, which this
replaces.
Reading the whole nvmem file needs the SM8350 keepout regions in the
qfprom driver; without them it resets the SoC.
Signed-off-by: Demeter Barna <me@xxxxxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 33 ++++++++++++++++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 903b2968c..d488c9d64 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -710,6 +710,18 @@ ipcc: mailbox@408000 {
#mbox-cells = <2>;
};
+ qfprom: efuse@784000 {
+ compatible = "qcom,sm8350-qfprom", "qcom,qfprom";
+ reg = <0 0x00784000 0 0x3000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gpu_speed_bin: gpu-speed-bin@17b {
+ reg = <0x17b 0x1>;
+ bits = <5 3>;
+ };
+ };
+
gpi_dma2: dma-controller@800000 {
compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0 0x00800000 0 0x60000>;
@@ -2057,6 +2069,9 @@ gpu: gpu@3d00000 {
operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
+
+ nvmem-cells = <&gpu_speed_bin>;
+ nvmem-cell-names = "speed_bin";
#cooling-cells = <2>;
status = "disabled";
@@ -2065,68 +2080,84 @@ gpu_zap_shader: zap-shader {
memory-region = <&pil_gpu_mem>;
};
- /* note: downstream checks gpu binning for 670 Mhz */
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
+ opp-peak-kBps = <12484375>;
+ opp-supported-hw = <0x2>;
+ };
+
opp-840000000 {
opp-hz = /bits/ 64 <840000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
opp-peak-kBps = <12484375>;
+ opp-supported-hw = <0x3>;
};
opp-778000000 {
opp-hz = /bits/ 64 <778000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
opp-peak-kBps = <12484375>;
+ opp-supported-hw = <0x3>;
};
opp-738000000 {
opp-hz = /bits/ 64 <738000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
opp-peak-kBps = <12484375>;
+ opp-supported-hw = <0x7>;
};
opp-676000000 {
opp-hz = /bits/ 64 <676000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
opp-peak-kBps = <10687500>;
+ opp-supported-hw = <0x7>;
};
opp-608000000 {
opp-hz = /bits/ 64 <608000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
opp-peak-kBps = <6074218>;
+ opp-supported-hw = <0x7>;
};
opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <6074218>;
+ opp-supported-hw = <0x7>;
};
opp-491000000 {
opp-hz = /bits/ 64 <491000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
opp-peak-kBps = <6074218>;
+ opp-supported-hw = <0x7>;
};
opp-443000000 {
opp-hz = /bits/ 64 <443000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <6074218>;
+ opp-supported-hw = <0x7>;
};
opp-379000000 {
opp-hz = /bits/ 64 <379000000>;
opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>;
opp-peak-kBps = <3972656>;
+ opp-supported-hw = <0x7>;
};
opp-315000000 {
opp-hz = /bits/ 64 <315000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-peak-kBps = <1761718>;
+ opp-supported-hw = <0x7>;
};
};
};
--
2.53.0