[PATCH v2 0/3] arm64/gcs: Store the GCSCRE0_EL1 register value not userspace mode

[Mark Brown]

At present we store the userspace GCS mode for a task using the prctl()
value set by userspace rather than the mode configuration written to
GCSCRE0_EL1 which means the register value needs to be generated on each
task switch when the new task uses GCS.  Since the mapping between the
two is easily reversable switch things around and store the value that
we need in the context switch path.

While reviewing this Catalin noticed a bug with handling of mode during
signal restore so fix that, then do a small refactoring to move code out
of the header, and finally make the switch.

Signed-off-by: Mark Brown <broonie@xxxxxxxxxx>
---
Changes in v2:
- Add a fix for failing to update the GCS mode.
- Always write GCSCRE0_EL1 when setting it for the current task.
- Use u64 rather than unsigned int to store the register value.
- WRITE_ONCE() when updating the stored register value.
- Link to v1: https://patch.msgid.link/20260917-arm64-gcs-store-gcscre0-v1-0-3c9fa9213bac@xxxxxxxxxx

---
Mark Brown (3):
      arm64/gcs: Ignore attempts to change GCS mode during signal return
      arm64/gcs: Move gcs_check_locked() out of the header
      arm64/gcs: Store GCSCRE0_EL1 values instead of userspace mode

 Documentation/arch/arm64/gcs.rst   | 13 +++------
 arch/arm64/include/asm/gcs.h       | 25 +++++-------------
 arch/arm64/include/asm/processor.h |  2 +-
 arch/arm64/kernel/process.c        | 11 ++++----
 arch/arm64/kernel/ptrace.c         |  4 +--
 arch/arm64/kernel/signal.c         | 28 +++-----------------
 arch/arm64/mm/gcs.c                | 54 +++++++++++++++++++++++++++++---------
 7 files changed, 63 insertions(+), 74 deletions(-)
---
base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
base-tree: git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm master
change-id: 20260911-arm64-gcs-store-gcscre0-2e3e246e6f7a

Best regards,
--  
Mark Brown <broonie@xxxxxxxxxx>