Re: [PATCH v7 2/3] i3c: master: Add Qualcomm I3C controller driver
From: kernel test robot
Date: Thu Nov 05 2026 - 09:53:44 EST
Hi Mukesh,
kernel test robot noticed the following build warnings:
[auto build test WARNING on i3c/i3c/next]
[also build test WARNING on linus/master v7.3 next-20261030]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Mukesh-Kumar-Savaliya/i3c-master-Add-Qualcomm-I3C-controller-driver/20261104-164609
base: https://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux.git i3c/next
patch link: https://lore.kernel.org/r/20261104111610.3739095-2-mukesh.savaliya%40oss.qualcomm.com
patch subject: [PATCH v7 2/3] i3c: master: Add Qualcomm I3C controller driver
config: sh-allyesconfig (https://download.01.org/0day-ci/archive/20261106/202611060055.y4Q35SU8-lkp@xxxxxxxxx/config)
compiler: sh4-linux-gcc (GCC) 16.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20261106/202611060055.y4Q35SU8-lkp@xxxxxxxxx/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@xxxxxxxxx>
| Closes: https://lore.kernel.org/oe-kbuild-all/202611060055.y4Q35SU8-lkp@xxxxxxxxx/
All warnings (new ones prefixed by >>):
drivers/i3c/master/i3c-qcom-geni.c: In function 'qcom_geni_i3c_conf':
drivers/i3c/master/i3c-qcom-geni.c:284:15: error: implicit declaration of function 'FIELD_PREP' [-Wimplicit-function-declaration]
284 | val = FIELD_PREP(CLK_DIV_VALUE_MASK, clk_idx->clk_div);
| ^~~~~~~~~~
drivers/i3c/master/i3c-qcom-geni.c: In function 'geni_i3c_irq':
>> drivers/i3c/master/i3c-qcom-geni.c:363:13: warning: variable 'm_stat_mask' set but not used [-Wunused-but-set-variable=]
363 | u32 m_stat_mask, dm_tx_st, dm_rx_st;
| ^~~~~~~~~~~
drivers/i3c/master/i3c-qcom-geni.c: In function 'i3c_geni_resources_init':
drivers/i3c/master/i3c-qcom-geni.c:977:15: error: too few arguments to function 'geni_icc_get'; expected 2, have 1
977 | ret = geni_icc_get(&gi3c->se);
| ^~~~~~~~~~~~
In file included from drivers/i3c/master/i3c-qcom-geni.c:19:
include/linux/soc/qcom/geni-se.h:576:5: note: declared here
576 | int geni_icc_get(struct geni_se *se, const char *icc_ddr);
| ^~~~~~~~~~~~
vim +/m_stat_mask +363 drivers/i3c/master/i3c-qcom-geni.c
359
360 static irqreturn_t geni_i3c_irq(int irq, void *dev)
361 {
362 struct geni_i3c_dev *gi3c = dev;
> 363 u32 m_stat_mask, dm_tx_st, dm_rx_st;
364 u32 m_stat, rx_st, dma_mode;
365
366 m_stat = readl_relaxed(gi3c->se.base + SE_GENI_M_IRQ_STATUS);
367 m_stat_mask = readl_relaxed(gi3c->se.base + SE_GENI_M_IRQ_EN);
368 rx_st = readl_relaxed(gi3c->se.base + SE_GENI_RX_FIFO_STATUS);
369 dm_tx_st = readl_relaxed(gi3c->se.base + SE_DMA_TX_IRQ_STAT);
370 dm_rx_st = readl_relaxed(gi3c->se.base + SE_DMA_RX_IRQ_STAT);
371 dma_mode = readl_relaxed(gi3c->se.base + SE_GENI_DMA_MODE_EN);
372
373 scoped_guard(spinlock, &gi3c->irq_lock) {
374 if (m_stat & SE_I3C_ERR || dm_rx_st & DM_I3C_CB_ERR) {
375 geni_i3c_handle_err(gi3c, m_stat);
376 /* Disable the TX Watermark interrupt to stop TX */
377 if (!dma_mode)
378 writel_relaxed(0, gi3c->se.base + SE_GENI_TX_WATERMARK_REG);
379 } else if (dma_mode) {
380 dev_dbg(gi3c->se.dev, "i3c dma tx:0x%x, dma rx:0x%x\n", dm_tx_st, dm_rx_st);
381 } else if ((m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) &&
382 !gi3c->cur_is_write && gi3c->cur_buf) {
383 /* FIFO RX handling */
384 u32 rxcnt = rx_st & RX_FIFO_WC_MSK;
385 int avail = rxcnt * 4;
386 int need = gi3c->cur_len - gi3c->cur_idx;
387 int n = min(need, avail);
388
389 if (n > 0) {
390 i3c_readl_fifo(gi3c->se.base + SE_GENI_RX_FIFOn,
391 gi3c->cur_buf + gi3c->cur_idx, n);
392 gi3c->cur_idx += n;
393 }
394 } else if ((m_stat & M_TX_FIFO_WATERMARK_EN) &&
395 gi3c->cur_is_write && gi3c->cur_buf) {
396 /* FIFO TX handling */
397 int avail = gi3c->tx_wm * 4;
398 int need = gi3c->cur_len - gi3c->cur_idx;
399 int n = min(need, avail);
400
401 if (n > 0) {
402 i3c_writel_fifo(gi3c->se.base + SE_GENI_TX_FIFOn,
403 (void *)(gi3c->cur_buf + gi3c->cur_idx), n);
404 gi3c->cur_idx += n;
405 }
406 }
407
408 if (!dma_mode && gi3c->cur_idx == gi3c->cur_len)
409 writel_relaxed(0, gi3c->se.base + SE_GENI_TX_WATERMARK_REG);
410 }
411
412 if (m_stat)
413 writel_relaxed(m_stat, gi3c->se.base + SE_GENI_M_IRQ_CLEAR);
414
415 if (dma_mode) {
416 if (dm_tx_st)
417 writel_relaxed(dm_tx_st, gi3c->se.base + SE_DMA_TX_IRQ_CLR);
418 if (dm_rx_st)
419 writel_relaxed(dm_rx_st, gi3c->se.base + SE_DMA_RX_IRQ_CLR);
420 }
421
422 /* if this is err with done-bit not set, handle that through timeout. */
423 if (m_stat & (M_CMD_DONE_EN | M_CMD_ABORT_EN)) {
424 writel_relaxed(0, gi3c->se.base + SE_GENI_TX_WATERMARK_REG);
425 complete(&gi3c->done);
426 } else if ((dm_tx_st & TX_DMA_DONE) || (dm_rx_st & (RX_DMA_DONE | RX_RESET_DONE))) {
427 complete(&gi3c->done);
428 }
429
430 return IRQ_HANDLED;
431 }
432
--
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