Re: [PATCH v16 11/18] PCI/CXL: Cache endpoint HDM state during PCI enumeration

[Srirangan Madhavan]

On 10/30/26 1:22 AM, Richard Cheng wrote:
> > -	return 0;
> > +	cxl_hdm_cache_set_dvsec_ctrl(pdev, ctrl);
> > +	return ret;
> >   }
> Hmmm this change the old behavior that when "ctrl & PCI_DVSEC_CXL_MEM_ENABLE == val",
> just return 1, it does cxl_hdm_cache_set_dvsec_ctrl() now, I wonder the reason ?
>
> Update software snapshot for the new design ?

Hi Richard,

Yes, it updates the software snapshot for the new design. A reset 
restores the cached DVSEC control value, so the cache has to match the 
live register even when MEM_ENABLE already matched. I added a comment 
saying so in v17.

I also made cxl_set_mem_enable() return -ENODEV on an all-ones read, so
that value is neither written back nor cached.

--
Regards,
Srirangan