Re: [PATCH] MIPS: Alchemy: Register interrupt chips with the IRQ core

[Thomas Bogendoerfer]

On Fri, Oct 16, 2026 at 11:15:59AM -0700, Florian Fainelli wrote:
> Alchemy initializes its interrupt chips through the set-type callbacks,
> which use irq_set_chip_handler_name_locked() to assign the chip and flow
> handler. This bypasses irq_set_chip() and its descriptor registration.
> 
> Since /proc/interrupts switched to iterating the IRQ descriptor maple tree,
> the statically allocated Alchemy descriptors are no longer found. On an
> MTX-1, the file contains only the CPU header and ERR counter even though
> the timer, serial, Ethernet and PCI wireless interrupts work.
> 
> Register each IC0/IC1 interrupt chip through irq_set_chip() before setting
> the initial trigger type. Do the same for the Au1300 GPIC. Keep the locked
> set-type callbacks for later trigger changes.
> 
> Fixes: 171cc0d9eed1 ("genirq/proc: Speed up /proc/interrupts iteration")
> Signed-off-by: Florian Fainelli <f.fainelli@xxxxxxxxx>
> ---
>  arch/mips/alchemy/common/irq.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)

applied to mips-fixes

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]