Re: [PATCH 2/2] clk: renesas: r9a09g056: Add ADC clocks and reset

[Lad, Prabhakar]

Hi Geert,

On Thu, Nov 5, 2026 at 2:52 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> On Thu, 5 Nov 2026 at 15:03, Lad, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > On Wed, Nov 4, 2026 at 4:45 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
> > > On Tue, 29 Sept 2026 at 13:39, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > >
> > > > Add clocks and reset entries for the ADC controller.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > >
> > > Thanks for your patch!
> > >
> > > Similar comments as for "[PATCH 1/2] clk: renesas: r9a09g057: Add ADC
> > > clocks and reset".
> > >
> > Ok, I will apply the same fixes here.
> >
> > > > --- a/drivers/clk/renesas/r9a09g056-cpg.c
> > > > +++ b/drivers/clk/renesas/r9a09g056-cpg.c
> > >
> > > > @@ -539,6 +556,10 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
> > > >                                                 BUS_MSTOP(3, BIT(4))),
> > > >         DEF_MOD("gpu_0_ace_clk",                CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
> > > >                                                 BUS_MSTOP(3, BIT(4))),
> > > > +       DEF_MOD("adc_0_pclk",                   CLK_PLLCM33_ADC_PCLK_DIV2, 16, 7, 8, 7,
> > > > +                                               BUS_MSTOP(3, BIT(9))),
> > > > +       DEF_MOD("adc_0_adclk",                  CLK_PLLCM33_ADC_ADCLK_GEAR, 16, 8, 8, 8,
> > > > +                                               BUS_MSTOP(3, BIT(9))),
> > Shall I also rename this adc_0 to adc_?
>
> OK, let's match the docs.
>
Ack.

> >
> > > >         DEF_MOD("tsu_0_pclk",                   CLK_QEXTAL, 16, 9, 8, 9,
> > > >                                                 BUS_MSTOP(5, BIT(2))),
> > > >         DEF_MOD("tsu_1_pclk",                   CLK_QEXTAL, 16, 10, 8, 10,
> > > > @@ -634,6 +655,7 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
> > > >         DEF_RST(13, 13, 6, 14),         /* GPU_0_RESETN */
> > > >         DEF_RST(13, 14, 6, 15),         /* GPU_0_AXI_RESETN */
> > > >         DEF_RST(13, 15, 6, 16),         /* GPU_0_ACE_RESETN */
> > > > +       DEF_RST(15, 6, 7, 7),           /* ADC_ADRST_N */
> > ADC_0/1/2_ADRST_N?
> >
and this I'll keep it as is (ADC_ADRST_N)

> > > >         DEF_RST(15, 7, 7, 8),           /* TSU_0_PRESETN */
> > > >         DEF_RST(15, 8, 7, 9),           /* TSU_1_PRESETN */
> > > >  };
> > >
> > > The lists of clock and reset signals (tables 4.4-2 and 4.4-3) claim
> > > there are 3 sets of clocks and resets, one for each ADC instance,
> > > but this does not seem to be reflected in the register bits?
> > >
> > The clock tree in r01uh1072ej0130-rzv2n (additional document).pdf
> > shows single clock is shared by all the three instances.
>
> I take your word on that (I only have the additional doc for RZ/V2H).
>
This has been tested on the V2N EVK connector J3.

Cheers,
Prabhakar