[PATCH v3 0/4] mmc: sdhci-cadence: SD6HC DDR50/DDR52 read-path tuning and fixes

[tze . yee . ng]

From: Tze Yee Ng <tze.yee.ng@xxxxxxxxxx>

This series enables the extended-read DDR modes - SD DDR50 and eMMC
DDR52 - on the Cadence SD6HC (SD/eMMC v6) PHY. Neither mode runs a host
tuning sequence (CMD19/CMD21), so the read path must be centred by
static, board/SoC-characterised PHY settings. Bringing it up on Agilex5
also exposed PHY issues affecting the existing tuned modes.

  - Patch 1: abort a failed tuning command on SD6HC. The software tuning
    loop never aborted a command that errored, so after a CMD21 command
    error the eMMC could stay in the Data state and time out the CMD6
    that HS400 selection issues next; mmc_send_abort_tuning() clears it
    (a no-op for SD).
  - Patch 2: program PHONY_DQS_TIMING (left 0 in all modes); in the
    extended-read DDR modes it must be the rebar pulse width in clk_phy
    cycles minus 1, else one DDR beat is duplicated.
  - Patch 3: document three optional SD6HC read-path properties for the
    extended-read DDR modes (SD DDR50, eMMC DDR52).
  - Patch 4: read those properties at probe and apply them in DDR50 and
    DDR52, and make the DQS_TIMING update clear USE_LPBK_DQS before
    reprogramming it so the loopback/phony selection takes effect.

The new cdns,ddr-* properties are unused in this series; they will be
consumed by the socfpga_agilex5_socdk and socfpga_agilex5_socdk_emmc
device trees, submitted as a separate series.

Tested on Agilex5 SoCDK: SD DDR50, eMMC DDR52 and eMMC HS400.

Signed-off-by: Tze Yee Ng <tze.yee.ng@xxxxxxxxxx>
---
Changes in v3:
- Patch 1: replaced the post-tuning PHY settle (v2 1/4) with aborting
  the failed tuning command. Added Suggested-by. (Tanmay Kathpalia)
- Patch 2: unchanged; retains Adrian's Acked-by.
- Patch 3: re-expressed cdns,ddr-read-dqs-delay-ps as
  cdns,ddr-read-dqs-delay - a count of DLL delay elements (0-255, each
  cdns,delay-element-ps wide) that maps 1:1 to the 8-bit PHY field -
  instead of a picosecond value; added $ref uint32 and maximum: 255,
  dropped the redundant minimum: 0, and used plain description: text.
  (Krzysztof Kozlowski)
- Patch 4: read cdns,ddr-read-dqs-delay directly as the delay-element
  count and write it to the 8-bit field, dropping the v2 ps->element
  conversion (divide by cdns,delay-element-ps) and the FIELD_MAX()
  clamp. Hoisted the repeated DDR-mode test to a local, removed the
  probe-time firmware-value warning, and unwrapped lines to 100 cols.
  (Adrian Hunter, Krzysztof Kozlowski)

- Link to v2: https://lore.kernel.org/all/cover.1791459448.git.tze.yee.ng@xxxxxxxxxx/
- Link to v1: https://lore.kernel.org/all/cover.1790074790.git.tze.yee.ng@xxxxxxxxxx/
---
To: Adrian Hunter <adrian.hunter@xxxxxxxxx>
To: Tanmay Kathpalia <tanmay.kathpalia@xxxxxxxxxx>
To: Ulf Hansson <ulfh@xxxxxxxxxx>
To: Rob Herring <robh@xxxxxxxxxx>
To: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>
To: Conor Dooley <conor+dt@xxxxxxxxxx>
Cc: linux-mmc@xxxxxxxxxxxxxxx
Cc: linux-kernel@xxxxxxxxxxxxxxx
Cc: devicetree@xxxxxxxxxxxxxxx

---
Tze Yee Ng (4):
      mmc: sdhci-cadence: abort failed tuning command on SD6HC
      mmc: sdhci-cadence6: program PHONY_DQS_TIMING for extended-read DDR
      dt-bindings: mmc: cdns,sd6hc: add SD6HC DDR50 read-path tuning
      mmc: sdhci-cadence6: read SD6HC DDR50 tuning from device tree

 .../devicetree/bindings/mmc/cdns,sd6hc.yaml        | 30 ++++++++++++
 drivers/mmc/host/sdhci-cadence-core.c              | 11 ++++-
 drivers/mmc/host/sdhci-cadence-phy-v6.c            | 57 +++++++++++++++++++++-
 3 files changed, 96 insertions(+), 2 deletions(-)
---
base-commit: 2febfc8acbf712439b6d30c99b108641d881fd75
change-id: 20261106-sd_cadence_ddr50_v3-35f970f31364

Best regards,
--  
Tze Yee Ng <tze.yee.ng@xxxxxxxxxx>