[PATCH v2 0/2] Add ADC clocks and reset for R9A09G05[6/7] SoCs

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Hi all,

This patch series adds the necessary ADC clocks and reset controls
for the RZ/V2H(P) and RZ/V2N SoCs.

v1->v2:
- Renamed adc_pclk_gear to pllcm33_adc_pclk_gear in patch #1
- Renamed adc_pclk_gear_div2 to pllcm33_adc_pclk_gear_div2 in patch #1
- Renamed adc_adclk_gear to pllcm33_adc_adclk_gear in patch #1
- Renamed ADC_ADRST_N to ADC_0_ADRST_N in patch #1
- Renamed adc_0_pclk to adc_pclk in patch #2
- Renamed adc_0_adclk to adc_adclk in patch #2

v0: https://lore.kernel.org/all/20260929113921.119489-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/

Cheers,
Prabhakar

Lad Prabhakar (2):
  clk: renesas: r9a09g057: Add ADC clocks and reset
  clk: renesas: r9a09g056: Add ADC clocks and reset

 drivers/clk/renesas/r9a09g056-cpg.c | 22 ++++++++++++++++++++++
 drivers/clk/renesas/r9a09g057-cpg.c | 22 ++++++++++++++++++++++
 drivers/clk/renesas/rzv2h-cpg.h     |  2 ++
 3 files changed, 46 insertions(+)

-- 
2.56.0