[PATCH] arm64: dts: imx93-11x11-frdm: add HDMI support

[Daniel Drake]

The FRDM i.MX93 board has HDMI output display path:

  LCDIF -> LDB (LVDS channel 0) -> IT6263 -> type-A HDMI connector

The product schematic shows that the reset line is on the PCAL6524 GPIO
expander port 2 pin 5 (which gpio-pca953x regards as offset 21), all of
the 3.3V supplies come from PMIC BUCK4, and all of the 1.8V supplies
from BUCK5.

Describe the bridge and the connector, link it to the LDB and enable
the LCDIF, LDB and media block control.

PLL and LCDIF clocks are initially set to support a fixed 74.25 MHz
pixel clock, which supports some common HDMI resolutions, similar to
the imx8mp.dtsi setup with its HDMI overlays. In future, we could allow
for dynamic PLL adjustment based on selected display mode, however this
first needs clock framework improvements to support coordination of
sibling clocks from different drivers.

Signed-off-by: Daniel Drake <ddrake@xxxxxxxxxxxx>
---
 arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts | 81 ++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts
index 6e8351d12016..6dd0977b8305 100644
--- a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts
@@ -9,6 +9,18 @@ / {
 	compatible = "fsl,imx93-11x11-frdm", "fsl,imx93";
 	model = "NXP i.MX93 11X11 FRDM board";
 
+	hdmi-connector {
+		compatible = "hdmi-connector";
+		label = "hdmi";
+		type = "a";
+
+		port {
+			hdmi_connector_in: endpoint {
+				remote-endpoint = <&it6263_out>;
+			};
+		};
+	};
+
 	reg_usdhc3_vmmc: regulator-usdhc3 {
 		compatible = "regulator-fixed";
 		regulator-name = "VPCIe_3V3";
@@ -38,6 +50,14 @@ &bluetooth {
 	vcc-supply = <&reg_usdhc3_vmmc>;
 };
 
+&lcdif {
+	status = "okay";
+};
+
+&ldb_lvds_ch0 {
+	remote-endpoint = <&it6263_lvds_in>;
+};
+
 &lpi2c1 {
 	pcal6408: gpio@20 {
 		compatible = "nxp,pcal6408";
@@ -47,6 +67,67 @@ pcal6408: gpio@20 {
 		reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>;
 		vcc-supply = <&buck5>;
 	};
+
+	hdmi@4c {
+		compatible = "ite,it6263";
+		reg = <0x4c>;
+		data-mapping = "jeida-24";
+		reset-gpios = <&pcal6524 21 GPIO_ACTIVE_LOW>;
+		ivdd-supply = <&buck5>;
+		ovdd-supply = <&buck4>;
+		txavcc18-supply = <&buck5>;
+		txavcc33-supply = <&buck4>;
+		pvcc1-supply = <&buck5>;
+		pvcc2-supply = <&buck5>;
+		avcc-supply = <&buck4>;
+		anvdd-supply = <&buck5>;
+		apvdd-supply = <&buck5>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				it6263_lvds_in: endpoint {
+					remote-endpoint = <&ldb_lvds_ch0>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				it6263_out: endpoint {
+					remote-endpoint = <&hdmi_connector_in>;
+				};
+			};
+		};
+	};
+};
+
+&lvds_bridge {
+	status = "okay";
+};
+
+&media_blk_ctrl {
+	assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>,
+			  <&clk IMX93_CLK_MEDIA_APB>,
+			  <&clk IMX93_CLK_VIDEO_PLL>,
+			  <&clk IMX93_CLK_MEDIA_DISP_PIX>;
+	assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>,
+				 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
+				 <0>,
+				 <&clk IMX93_CLK_VIDEO_PLL>;
+	/*
+	 * Set IMX93_CLK_MEDIA_DISP_PIX rate to 74250000Hz to accommodate
+	 * IMX93_CLK_VIDEO_PLL rate at 519750000Hz in a rate table.
+	 * The resultant 74.25MHz pixel clock supports some common HDMI
+	 * resolutions including 1280x720@60 and 1920x1080@30.
+	 */
+	assigned-clock-rates = <400000000>, <133333333>,
+			       <519750000>, <74250000>;
+	status = "okay";
 };
 
 &mqs1 {

---
base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
change-id: 20261106-imx93-frdm-hdmi-73f6a394ae51

Best regards,
-- 
Daniel Drake <ddrake@xxxxxxxxxxxx>