Re: [PATCH v2 0/2] arm64: dts: freescale: Re-enable A72 cluster on i.MX8QM boards

[Frank . Li]

From: Frank Li <Frank.Li@xxxxxxx>


On Fri, 23 Oct 2026 10:56:58 +0800, Peng Fan (OSS) wrote:
> The ERR050104 cache coherency workaround for the NXP i.MX8QuadMax and
> i.MX8QuadPlus SoCs has been merged upstream as commit d44e08dab27d
> ("arm64: errata: Add NXP i.MX8QM/8QP workaround for A53 cache coherency
> issue").
> 
> The workaround addresses a hardware defect where the upper address bits
> of the ARADDR and ACADDR buses within the Cortex-A53 subsystem were
> incorrectly connected, causing TLBI and IC maintenance operations
> exchanged between the A53 and A72 clusters to be corrupted.
> 
> [...]

Applied, thanks!

[1/2] arm64: dts: imx8qm-mek: Re-enable A72 cluster after ERR050104 workaround
      commit: 38aecc5bf9de1e26dcc8fc0a5a6882593248b293
[2/2] Revert "arm64: dts: imx8qm-tqma8qm-mba8x: Disable Cortex-A72 cluster"
      commit: df30ccf2cf43dbe0f1766eb47fb84c46f6401ffe

Best regards,
-- 
Frank Li <Frank.Li@xxxxxxx>